| Message ID | 20230127230123.941930-1-greenjustin@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/mediatek: Add support for AR30 and BA30 | expand |
Hi, Justin: Justin Green <greenjustin@chromium.org> 於 2023年1月28日 週六 上午7:01寫道： > > Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver. > > Tested using "modetest -P" on an MT8195. > > Signed-off-by: Justin Green <greenjustin@chromium.org> > --- > v2: > * Rebase and resolve merge conflicts with the AFBC patch. > v3: > * Moved 10-bit support detection to mtk_disk_ovl.c > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 37 +++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 ++++++ > drivers/gpu/drm/mediatek/mtk_drm_plane.c | 37 ++++++++++++++++++--- > drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 +- > 7 files changed, 84 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index 33e61a136bbc..b75139da3032 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -96,6 +96,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev, > void mtk_ovl_unregister_vblank_cb(struct device *dev); > void mtk_ovl_enable_vblank(struct device *dev); > void mtk_ovl_disable_vblank(struct device *dev); > +int mtk_ovl_supports_10bit(struct device *dev); > > void mtk_rdma_bypass_shadow(struct device *dev); > int mtk_rdma_clk_enable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 84daeaffab6a..412a749a509e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -41,6 +41,7 @@ > #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) > #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) > #define DISP_REG_OVL_ADDR_MT2701 0x0040 > +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 > #define DISP_REG_OVL_ADDR_MT8173 0x0f40 > #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) > #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) > @@ -61,6 +62,10 @@ > 0 : OVL_CON_CLRFMT_RGB) > #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ > OVL_CON_CLRFMT_RGB : 0) > +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) > +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) > +#define OVL_CON_CLRFMT_8_BIT 0x00 > +#define OVL_CON_CLRFMT_10_BIT 0x01 > #define OVL_CON_AEN BIT(8) > #define OVL_CON_ALPHA 0xff > #define OVL_CON_VIRT_FLIP BIT(9) > @@ -73,6 +78,7 @@ struct mtk_disp_ovl_data { > bool fmt_rgb565_is_0; > bool smi_id_en; > bool supports_afbc; > + bool supports_10bit; > }; > > /* > @@ -188,6 +194,26 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt > DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); > } > > +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); > + unsigned int reg; > + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; > + > + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); > + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); > + > + if (format == DRM_FORMAT_RGBA1010102 || > + format == DRM_FORMAT_BGRA1010102 || > + format == DRM_FORMAT_ARGB2101010) > + bit_depth = OVL_CON_CLRFMT_10_BIT; > + > + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); > + > + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT); > +} > + > void mtk_ovl_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -216,6 +242,13 @@ unsigned int mtk_ovl_supported_rotations(struct device *dev) > DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; > } > > +int mtk_ovl_supports_10bit(struct device *dev) > +{ > + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); > + > + return ovl->data->supports_10bit; > +} > + > int mtk_ovl_layer_check(struct device *dev, unsigned int idx, > struct mtk_plane_state *mtk_state) > { > @@ -302,9 +335,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) > return OVL_CON_CLRFMT_ARGB8888; > case DRM_FORMAT_BGRX8888: > case DRM_FORMAT_BGRA8888: > + case DRM_FORMAT_BGRA1010102: > return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_XRGB8888: > case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_ARGB2101010: > return OVL_CON_CLRFMT_RGBA8888; > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_ABGR8888: > @@ -388,6 +423,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, > &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); > } > > + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); > mtk_ovl_layer_on(dev, idx, cmdq_pkt); > } > > @@ -541,6 +577,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { > .fmt_rgb565_is_0 = true, > .smi_id_en = true, > .supports_afbc = true, > + .supports_10bit = true, > }; > > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 112615817dcb..9f162c9b504a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -856,7 +856,8 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, > BIT(pipe), > mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, > num_planes), > - mtk_ddp_comp_supported_rotations(comp)); > + mtk_ddp_comp_supported_rotations(comp), > + mtk_ddp_comp_supports_10bit(comp)); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 6b6d5335c834..708963c613d3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -359,6 +359,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .layer_config = mtk_ovl_layer_config, > .bgclr_in_on = mtk_ovl_bgclr_in_on, > .bgclr_in_off = mtk_ovl_bgclr_in_off, > + .supports_10bit = mtk_ovl_supports_10bit, > }; > > static const struct mtk_ddp_comp_funcs ddp_postmask = { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 2d0052c23dcb..18ec5dca2337 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -71,6 +71,7 @@ struct mtk_ddp_comp_funcs { > void (*bgclr_in_off)(struct device *dev); > void (*ctm_set)(struct device *dev, > struct drm_crtc_state *state); > + int (*supports_10bit)(struct device *dev); > }; > > struct mtk_ddp_comp { > @@ -151,6 +152,15 @@ unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp) > return 0; > } > > +static inline > +int mtk_ddp_comp_supports_10bit(struct mtk_ddp_comp *comp) > +{ > + if (comp->funcs && comp->funcs->supports_10bit) > + return comp->funcs->supports_10bit; > + > + return 0; > +} > + > static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) > { > if (comp->funcs && comp->funcs->layer_nr) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c > index d54fbf34b000..e94a07cdda32 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c > @@ -19,7 +19,7 @@ > #include "mtk_drm_gem.h" > #include "mtk_drm_plane.h" > > -static const u32 formats[] = { > +static const u32 default_formats[] = { > DRM_FORMAT_XRGB8888, > DRM_FORMAT_ARGB8888, > DRM_FORMAT_BGRX8888, > @@ -41,6 +41,22 @@ static const u64 modifiers[] = { > DRM_FORMAT_MOD_INVALID, > }; > > +static const u32 formats_with_10bit_cap[] = { > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_ARGB8888, > + DRM_FORMAT_ARGB2101010, > + DRM_FORMAT_BGRX8888, > + DRM_FORMAT_BGRA8888, > + DRM_FORMAT_BGRA1010102, > + DRM_FORMAT_ABGR8888, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_RGB888, > + DRM_FORMAT_BGR888, > + DRM_FORMAT_RGB565, > + DRM_FORMAT_UYVY, > + DRM_FORMAT_YUYV, > +}; I would like to move formats_with_10bit_cap[] & formats[] to ovl/rdma driver and rename formats[] to formats_mt8173[] and rename formats_with_10bit_cap[] to formats_mt8195[]. And change comp->funcs->supports_10bit() to comp->funcs->get_formats(). Regards, Chun-Kuang. > + > static void mtk_plane_reset(struct drm_plane *plane) > { > struct mtk_plane_state *state; > @@ -315,13 +331,24 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { > > int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, > unsigned long possible_crtcs, enum drm_plane_type type, > - unsigned int supported_rotations) > + unsigned int supported_rotations, bool supports_10bit) > { > int err; > > - err = drm_universal_plane_init(dev, plane, possible_crtcs, > - &mtk_plane_funcs, formats, > - ARRAY_SIZE(formats), modifiers, type, NULL); > + if (supports_10bit) { > + err = drm_universal_plane_init(dev, plane, possible_crtcs, > + &mtk_plane_funcs, > + formats_with_10bit_cap, > + ARRAY_SIZE(formats_with_10bit_cap), > + modifiers, type, NULL); > + } else { > + err = drm_universal_plane_init(dev, plane, possible_crtcs, > + &mtk_plane_funcs, > + default_formats, > + ARRAY_SIZE(default_formats), > + modifiers, type, NULL); > + } > + > if (err) { > DRM_ERROR("failed to initialize plane\n"); > return err; > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h > index 8f39011cdbfc..d3e6f29a1e25 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h > @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state) > > int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, > unsigned long possible_crtcs, enum drm_plane_type type, > - unsigned int supported_rotations); > + unsigned int supported_rotations, bool supports_10bit); > > #endif > -- > 2.39.1.456.gfc5497dd1b-goog >
Hi Justin,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.2-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Justin-Green/drm-mediatek-Add-support-for-AR30-and-BA30/20230128-112134
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230127230123.941930-1-greenjustin%40google.com
patch subject: [PATCH v3] drm/mediatek: Add support for AR30 and BA30
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20230129/202301291906.Az5NHf9w-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/c32525cf66e7bbf4e798aef3aafbf88dee5d049c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Justin-Green/drm-mediatek-Add-support-for-AR30-and-BA30/20230128-112134
git checkout c32525cf66e7bbf4e798aef3aafbf88dee5d049c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/mediatek/ sound/soc/samsung/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/mediatek/mtk_drm_crtc.h:10,
from drivers/gpu/drm/mediatek/mtk_disp_aal.c:15:
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h: In function 'mtk_ddp_comp_supports_10bit':
>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h:159:35: warning: returning 'int (*)(struct device *)' from a function with return type 'int' makes integer from pointer without a cast [-Wint-conversion]
159 | return comp->funcs->supports_10bit;
| ~~~~~~~~~~~^~~~~~~~~~~~~~~~
vim +159 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
154
155 static inline
156 int mtk_ddp_comp_supports_10bit(struct mtk_ddp_comp *comp)
157 {
158 if (comp->funcs && comp->funcs->supports_10bit)
> 159 return comp->funcs->supports_10bit;
160
161 return 0;
162 }
163
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 33e61a136bbc..b75139da3032 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -96,6 +96,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +int mtk_ovl_supports_10bit(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 84daeaffab6a..412a749a509e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -73,6 +78,7 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + bool supports_10bit; }; /* @@ -188,6 +194,26 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -216,6 +242,13 @@ unsigned int mtk_ovl_supported_rotations(struct device *dev) DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } +int mtk_ovl_supports_10bit(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->supports_10bit; +} + int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state) { @@ -302,9 +335,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -388,6 +423,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); } @@ -541,6 +577,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, + .supports_10bit = true, }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 112615817dcb..9f162c9b504a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -856,7 +856,8 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, BIT(pipe), mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, num_planes), - mtk_ddp_comp_supported_rotations(comp)); + mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_supports_10bit(comp)); if (ret) return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6b6d5335c834..708963c613d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -359,6 +359,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .layer_config = mtk_ovl_layer_config, .bgclr_in_on = mtk_ovl_bgclr_in_on, .bgclr_in_off = mtk_ovl_bgclr_in_off, + .supports_10bit = mtk_ovl_supports_10bit, }; static const struct mtk_ddp_comp_funcs ddp_postmask = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2d0052c23dcb..18ec5dca2337 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -71,6 +71,7 @@ struct mtk_ddp_comp_funcs { void (*bgclr_in_off)(struct device *dev); void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); + int (*supports_10bit)(struct device *dev); }; struct mtk_ddp_comp { @@ -151,6 +152,15 @@ unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp) return 0; } +static inline +int mtk_ddp_comp_supports_10bit(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->supports_10bit) + return comp->funcs->supports_10bit; + + return 0; +} + static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->layer_nr) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index d54fbf34b000..e94a07cdda32 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -19,7 +19,7 @@ #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -static const u32 formats[] = { +static const u32 default_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_BGRX8888, @@ -41,6 +41,22 @@ static const u64 modifiers[] = { DRM_FORMAT_MOD_INVALID, }; +static const u32 formats_with_10bit_cap[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + static void mtk_plane_reset(struct drm_plane *plane) { struct mtk_plane_state *state; @@ -315,13 +331,24 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations) + unsigned int supported_rotations, bool supports_10bit) { int err; - err = drm_universal_plane_init(dev, plane, possible_crtcs, - &mtk_plane_funcs, formats, - ARRAY_SIZE(formats), modifiers, type, NULL); + if (supports_10bit) { + err = drm_universal_plane_init(dev, plane, possible_crtcs, + &mtk_plane_funcs, + formats_with_10bit_cap, + ARRAY_SIZE(formats_with_10bit_cap), + modifiers, type, NULL); + } else { + err = drm_universal_plane_init(dev, plane, possible_crtcs, + &mtk_plane_funcs, + default_formats, + ARRAY_SIZE(default_formats), + modifiers, type, NULL); + } + if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 8f39011cdbfc..d3e6f29a1e25 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state) int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations); + unsigned int supported_rotations, bool supports_10bit); #endif
Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver. Tested using "modetest -P" on an MT8195. Signed-off-by: Justin Green <greenjustin@chromium.org> --- v2: * Rebase and resolve merge conflicts with the AFBC patch. v3: * Moved 10-bit support detection to mtk_disk_ovl.c drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 37 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 ++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 37 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 +- 7 files changed, 84 insertions(+), 7 deletions(-)