| Message ID | 20230127182558.2416400-11-atishp@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM perf support | expand |
On Fri, Jan 27, 2023 at 11:56 PM Atish Patra <atishp@rivosinc.com> wrote: > > Any guest must not get access to any hpmcounter including cycle/instret > without any checks. We achieve that by disabling all the bits except TM > bit in hcounteren. > > However, instret and cycle access for guest user space can be enabled > upon explicit request (via ONE REG) or on first trap from VU mode > to maintain ABI requirement in the future. This patch doesn't support > that as ONE REG interface is not settled yet. > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/kvm/main.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c > index 58c5489..c5d400f 100644 > --- a/arch/riscv/kvm/main.c > +++ b/arch/riscv/kvm/main.c > @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) > hideleg |= (1UL << IRQ_VS_EXT); > csr_write(CSR_HIDELEG, hideleg); > > - csr_write(CSR_HCOUNTEREN, -1UL); > + /* VS should access only the time counter directly. Everything else should trap */ > + csr_write(CSR_HCOUNTEREN, 0x02); > > csr_write(CSR_HVIP, 0); > > -- > 2.25.1 >
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 58c5489..c5d400f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) hideleg |= (1UL << IRQ_VS_EXT); csr_write(CSR_HIDELEG, hideleg); - csr_write(CSR_HCOUNTEREN, -1UL); + /* VS should access only the time counter directly. Everything else should trap */ + csr_write(CSR_HCOUNTEREN, 0x02); csr_write(CSR_HVIP, 0);