[00/24] Add basic ACPI support for RISC-V

Message ID	20230130182225.2471414-1-sunilvl@ventanamicro.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Sunil V L <sunilvl@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Jonathan Corbet <corbet@lwn.net> Subject: [PATCH 00/24] Add basic ACPI support for RISC-V Date: Mon, 30 Jan 2023 23:52:01 +0530 Message-Id: <20230130182225.2471414-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: list Cc: Anup Patel <apatel@ventanamicro.com>, linux-doc@vger.kernel.org, Atish Patra <atishp@rivosinc.com>, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, Andrew Jones <ajones@ventanamicro.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Add basic ACPI support for RISC-V \| expand [00/24] Add basic ACPI support for RISC-V [01/24] riscv: move sbi_init() earlier before jump_label_init() [02/24] ACPICA: MADT: Add RISC-V INTC interrupt controller [03/24] ACPICA: Add structure definitions for RISC-V RHCT [04/24] RISC-V: ACPI: Add empty headers to enable ACPI core [05/24] RISC-V: ACPI: Add basic functions to build ACPI core [06/24] RISC-V: ACPI: Add PCI functions to build ACPI core [07/24] RISC-V: ACPI: Enable ACPI build infrastructure [08/24] ACPI: Enable ACPI_PROCESSOR for RISC-V [09/24] ACPI: OSL: Make should_use_kmap() 0 for RISC-V. [10/24] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid [11/24] RISC-V: ACPI: irqchip/riscv-intc: Add ACPI support [12/24] RISC-V: ACPI: smpboot: Create wrapper smp_setup() [13/24] RISC-V: ACPI: smpboot: Add ACPI support in smp_setup() [14/24] RISC-V: ACPI: smpboot: Add function to retrieve the hartid [15/24] clocksource/timer-riscv: Refactor riscv_timer_init_dt() [16/24] RISC-V: ACPI: clocksource/timer-riscv: Add ACPI support [17/24] ACPI: RISC-V: drivers/acpi: Add RHCT related code [18/24] RISC-V: ACPI: time.c: Add ACPI support for time_init() [19/24] RISC-V: ACPI: cpufeature: Add ACPI support in riscv_fill_hwcap() [20/24] RISC-V: ACPI: cpu: Enable cpuinfo for ACPI systems [21/24] RISC-V: ACPI: Add ACPI initialization in setup_arch() [22/24] RISC-V: ACPI: Enable ACPI in defconfig [23/24] MAINTAINERS: Add entry for drivers/acpi/riscv [24/24] Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter

Message ID

20230130182225.2471414-1-sunilvl@ventanamicro.com (mailing list archive)

Headers

From: Sunil V L <sunilvl@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jonathan Corbet <corbet@lwn.net>
Subject: [PATCH 00/24] Add basic ACPI support for RISC-V
Date: Mon, 30 Jan 2023 23:52:01 +0530
Message-Id: <20230130182225.2471414-1-sunilvl@ventanamicro.com>
MIME-Version: 1.0
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Cc: Anup Patel <apatel@ventanamicro.com>, linux-doc@vger.kernel.org,
 Atish Patra <atishp@rivosinc.com>, linux-kernel@vger.kernel.org,
 linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
 Andrew Jones <ajones@ventanamicro.com>
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

Add basic ACPI support for RISC-V | expand

Message

Sunil V L Jan. 30, 2023, 6:22 p.m. UTC

This patch series enables the basic ACPI infrastructure for RISC-V.
Supporting external interrupt controllers is in progress and hence it is
tested using polling based HVC SBI console and RAM disk.

The series depends on Anup's IPI improvement series.
https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17

These changes are available at
https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17

Testing:
1) Build Qemu with ACPI support using below branch
https://github.com/vlsunil/qemu/tree/acpi_b1_us_review

2) Build EDK2 as per instructions in
https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support

3) Build Linux after enabling SBI HVC and SBI earlycon
CONFIG_RISCV_SBI_V01=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HVC_RISCV_SBI=y

4) Build buildroot.

Run with below command.
qemu-system-riscv64   -nographic \
-drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
-machine virt,acpi=on -smp 16 -m 2G \
-kernel arch/riscv/boot/Image \
-initrd buildroot/output/images/rootfs.cpio \
-append "root=/dev/ram ro console=hvc0 earlycon=sbi"

Jisheng Zhang (1):
  riscv: move sbi_init() earlier before jump_label_init()

Sunil V L (23):
  ACPICA: MADT: Add RISC-V INTC interrupt controller
  ACPICA: Add structure definitions for RISC-V RHCT
  RISC-V: ACPI: Add empty headers to enable ACPI core
  RISC-V: ACPI: Add basic functions to build ACPI core
  RISC-V: ACPI: Add PCI functions to build ACPI core
  RISC-V: ACPI: Enable ACPI build infrastructure
  ACPI: Enable ACPI_PROCESSOR for RISC-V
  ACPI: OSL: Make should_use_kmap() 0 for RISC-V.
  ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
  RISC-V: ACPI: irqchip/riscv-intc: Add ACPI support
  RISC-V: ACPI: smpboot: Create wrapper smp_setup()
  RISC-V: ACPI: smpboot: Add ACPI support in smp_setup()
  RISC-V: ACPI: smpboot: Add function to retrieve the hartid
  clocksource/timer-riscv: Refactor riscv_timer_init_dt()
  RISC-V: ACPI: clocksource/timer-riscv: Add ACPI support
  ACPI: RISC-V: drivers/acpi: Add RHCT related code
  RISC-V: ACPI: time.c: Add ACPI support for time_init()
  RISC-V: ACPI: cpufeature: Add ACPI support in riscv_fill_hwcap()
  RISC-V: ACPI: cpu: Enable cpuinfo for ACPI systems
  RISC-V: ACPI: Add ACPI initialization in setup_arch()
  RISC-V: ACPI: Enable ACPI in defconfig
  MAINTAINERS: Add entry for drivers/acpi/riscv
  Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter

 .../admin-guide/kernel-parameters.txt         |   6 +-
 MAINTAINERS                                   |   7 +
 arch/riscv/Kconfig                            |   5 +
 arch/riscv/configs/defconfig                  |   4 +
 arch/riscv/include/asm/acenv.h                |  17 ++
 arch/riscv/include/asm/acpi.h                 |  87 +++++++++
 arch/riscv/include/asm/cpu.h                  |   9 +
 arch/riscv/kernel/Makefile                    |   3 +
 arch/riscv/kernel/acpi.c                      | 178 ++++++++++++++++++
 arch/riscv/kernel/cpu.c                       |  36 +++-
 arch/riscv/kernel/cpufeature.c                |  45 ++++-
 arch/riscv/kernel/pci.c                       | 173 +++++++++++++++++
 arch/riscv/kernel/setup.c                     |  21 ++-
 arch/riscv/kernel/smpboot.c                   |  99 +++++++++-
 arch/riscv/kernel/time.c                      |  25 ++-
 drivers/acpi/Kconfig                          |   2 +-
 drivers/acpi/Makefile                         |   2 +
 drivers/acpi/osl.c                            |   2 +-
 drivers/acpi/processor_core.c                 |  28 +++
 drivers/acpi/riscv/Makefile                   |   2 +
 drivers/acpi/riscv/rhct.c                     |  93 +++++++++
 drivers/clocksource/timer-riscv.c             |  88 ++++-----
 drivers/irqchip/irq-riscv-intc.c              |  79 ++++++--
 include/acpi/actbl2.h                         |  69 ++++++-
 24 files changed, 994 insertions(+), 86 deletions(-)
 create mode 100644 arch/riscv/include/asm/acenv.h
 create mode 100644 arch/riscv/include/asm/acpi.h
 create mode 100644 arch/riscv/include/asm/cpu.h
 create mode 100644 arch/riscv/kernel/acpi.c
 create mode 100644 arch/riscv/kernel/pci.c
 create mode 100644 drivers/acpi/riscv/Makefile
 create mode 100644 drivers/acpi/riscv/rhct.c

Comments

Rafael J. Wysocki Jan. 30, 2023, 7:11 p.m. UTC | #1

On Mon, Jan 30, 2023 at 7:22 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> This patch series enables the basic ACPI infrastructure for RISC-V.
> Supporting external interrupt controllers is in progress and hence it is
> tested using polling based HVC SBI console and RAM disk.
>
> The series depends on Anup's IPI improvement series.
> https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17
>
> These changes are available at
> https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17
>
> Testing:
> 1) Build Qemu with ACPI support using below branch
> https://github.com/vlsunil/qemu/tree/acpi_b1_us_review
>
> 2) Build EDK2 as per instructions in
> https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support
>
> 3) Build Linux after enabling SBI HVC and SBI earlycon
> CONFIG_RISCV_SBI_V01=y
> CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
> CONFIG_HVC_RISCV_SBI=y
>
> 4) Build buildroot.
>
> Run with below command.
> qemu-system-riscv64   -nographic \
> -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
> -machine virt,acpi=on -smp 16 -m 2G \
> -kernel arch/riscv/boot/Image \
> -initrd buildroot/output/images/rootfs.cpio \
> -append "root=/dev/ram ro console=hvc0 earlycon=sbi"
>
> Jisheng Zhang (1):
>   riscv: move sbi_init() earlier before jump_label_init()
>
> Sunil V L (23):
>   ACPICA: MADT: Add RISC-V INTC interrupt controller
>   ACPICA: Add structure definitions for RISC-V RHCT
>   RISC-V: ACPI: Add empty headers to enable ACPI core
>   RISC-V: ACPI: Add basic functions to build ACPI core
>   RISC-V: ACPI: Add PCI functions to build ACPI core
>   RISC-V: ACPI: Enable ACPI build infrastructure
>   ACPI: Enable ACPI_PROCESSOR for RISC-V
>   ACPI: OSL: Make should_use_kmap() 0 for RISC-V.
>   ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
>   RISC-V: ACPI: irqchip/riscv-intc: Add ACPI support
>   RISC-V: ACPI: smpboot: Create wrapper smp_setup()
>   RISC-V: ACPI: smpboot: Add ACPI support in smp_setup()
>   RISC-V: ACPI: smpboot: Add function to retrieve the hartid
>   clocksource/timer-riscv: Refactor riscv_timer_init_dt()
>   RISC-V: ACPI: clocksource/timer-riscv: Add ACPI support
>   ACPI: RISC-V: drivers/acpi: Add RHCT related code
>   RISC-V: ACPI: time.c: Add ACPI support for time_init()
>   RISC-V: ACPI: cpufeature: Add ACPI support in riscv_fill_hwcap()
>   RISC-V: ACPI: cpu: Enable cpuinfo for ACPI systems
>   RISC-V: ACPI: Add ACPI initialization in setup_arch()
>   RISC-V: ACPI: Enable ACPI in defconfig
>   MAINTAINERS: Add entry for drivers/acpi/riscv
>   Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter

The series looks fine to me from the ACPI perspective, so please feel
free to add

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

to it and route it via RISC-V.

Thanks!

Conor Dooley Feb. 8, 2023, 6:28 p.m. UTC | #2

Hey Sunil,

On Mon, Jan 30, 2023 at 11:52:01PM +0530, Sunil V L wrote:
> This patch series enables the basic ACPI infrastructure for RISC-V.
> Supporting external interrupt controllers is in progress and hence it is
> tested using polling based HVC SBI console and RAM disk.
> 
> The series depends on Anup's IPI improvement series.
> https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17

In the future, please provide links to patchsets rather than "random"
git trees.

> Jisheng Zhang (1):
>   riscv: move sbi_init() earlier before jump_label_init()
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

What has this patch got to do with your series? Just something that was
sitting in your tree?

If you need this, it'd be ideal if you would submit *with* the R-b tags
it appears to have had by v6 [1] & add the reason that you need to move
it to the commit message.
In Jisheng's series that was obvious, but this is a significantly larger
series and it is hard to spot your reasoning for it.

Cheers,
Conor.

Conor Dooley Feb. 8, 2023, 6:50 p.m. UTC | #3

On Wed, Feb 08, 2023 at 06:28:15PM +0000, Conor Dooley wrote:
> Hey Sunil,
> 
> On Mon, Jan 30, 2023 at 11:52:01PM +0530, Sunil V L wrote:
> > This patch series enables the basic ACPI infrastructure for RISC-V.
> > Supporting external interrupt controllers is in progress and hence it is
> > tested using polling based HVC SBI console and RAM disk.
> > 
> > The series depends on Anup's IPI improvement series.
> > https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17
> 
> In the future, please provide links to patchsets rather than "random"
> git trees.
> 
> > Jisheng Zhang (1):
> >   riscv: move sbi_init() earlier before jump_label_init()
>     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> What has this patch got to do with your series? Just something that was
> sitting in your tree?
> 
> If you need this, it'd be ideal if you would submit *with* the R-b tags
> it appears to have had by v6 [1] & add the reason that you need to move
> it to the commit message.
> In Jisheng's series that was obvious, but this is a significantly larger
> series and it is hard to spot your reasoning for it.

Apologies, I forgot to provide the link!
https://lore.kernel.org/all/20220821140918.3613-1-jszhang@kernel.org/

Cheers,
Conor.

Sunil V L Feb. 13, 2023, 4:51 a.m. UTC | #4

Hi Conor,

On Wed, Feb 08, 2023 at 06:50:39PM +0000, Conor Dooley wrote:
> On Wed, Feb 08, 2023 at 06:28:15PM +0000, Conor Dooley wrote:
> > Hey Sunil,
> > 
> > On Mon, Jan 30, 2023 at 11:52:01PM +0530, Sunil V L wrote:
> > > This patch series enables the basic ACPI infrastructure for RISC-V.
> > > Supporting external interrupt controllers is in progress and hence it is
> > > tested using polling based HVC SBI console and RAM disk.
> > > 
> > > The series depends on Anup's IPI improvement series.
> > > https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17
> > 
> > In the future, please provide links to patchsets rather than "random"
> > git trees.
> > 
> > > Jisheng Zhang (1):
> > >   riscv: move sbi_init() earlier before jump_label_init()
> >     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > 
> > What has this patch got to do with your series? Just something that was
> > sitting in your tree?
> > 
> > If you need this, it'd be ideal if you would submit *with* the R-b tags
> > it appears to have had by v6 [1] & add the reason that you need to move
> > it to the commit message.
> > In Jisheng's series that was obvious, but this is a significantly larger
> > series and it is hard to spot your reasoning for it.
> 
> Apologies, I forgot to provide the link!
> https://lore.kernel.org/all/20220821140918.3613-1-jszhang@kernel.org/
> 

First of all, thank you very much for your detailed review!!. Will address
your comments in the next revision of the series I am preparing to send this
week.

This patch from Jisheng is required to enable ACPI for the same reason.
sbi_init() should be called before jump_label_init(). Otherwise, I hit a
panic like below.

[   0.000000] efi: seeding entropy pool
 [   0.000000] sbi_remote_fence_i: Enter for cpu_mask = 0000000000000000
 [   0.000000] Kernel panic - not syncing: __sbi_rfence is called before sbi_init!!!
 [   0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.19.0-rc3-00079-gd3ee951eeea1-dirty #3
 [   0.000000] Call Trace:
 [   0.000000] [<ffffffff80005900>] dump_backtrace+0x1c/0x24
 [   0.000000] [<ffffffff8072a83e>] show_stack+0x2c/0x38
 [   0.000000] [<ffffffff8072fe7c>] dump_stack_lvl+0x40/0x58
 [   0.000000] [<ffffffff8072fea8>] dump_stack+0x14/0x1c
 [   0.000000] [<ffffffff8072ae4a>] panic+0x106/0x2c6
 [   0.000000] [<ffffffff8072a964>] sbi_remote_fence_i+0x32/0x4a
 [   0.000000] [<ffffffff80009c22>] flush_icache_all+0x1a/0x44
 [   0.000000] [<ffffffff8000622a>] patch_text_nosync+0x1e/0x2a
 [   0.000000] [<ffffffff800084da>] arch_jump_label_transform+0x48/0xd0
 [   0.000000] [<ffffffff801013ee>] __jump_label_update+0x82/0xd4
 [   0.000000] [<ffffffff801014bc>] jump_label_update+0x7c/0xca
 [   0.000000] [<ffffffff80101b5c>] static_key_enable_cpuslocked+0x70/0x9c
 [   0.000000] [<ffffffff80101b9e>] static_key_enable+0x16/0x24
 [   0.000000] [<ffffffff80730c16>] crng_set_ready+0x18/0x20
 [   0.000000] [<ffffffff80022f06>] execute_in_process_context+0x3e/0x92
 [   0.000000] [<ffffffff80730dc8>] _credit_init_bits+0x9c/0x140
 [   0.000000] [<ffffffff80827024>] add_bootloader_randomness+0x3e/0x48
 [   0.000000] [<ffffffff8082c434>] efi_config_parse_tables+0x114/0x21c
 [   0.000000] [<ffffffff8082dd18>] efi_init+0x11e/0x22a
 [   0.000000] [<ffffffff80803256>] setup_arch+0xc8/0x5fa
 [   0.000000] [<ffffffff80800716>] start_kernel+0x88/0x74e
 [   0.000000] ---[ end Kernel panic - not syncing: __sbi_rfence is called before sbi_init!!! ]---


Yes, I missed V6 of Jishang. Will update it. I will also use public
patchset linkgs.

Thanks!
Sunil