diff mbox series

[v2] drm/i915/gt: Add sysfs RAPL PL1 interface

Message ID 20230131062550.11901-1-sujaritha.sundaresan@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2] drm/i915/gt: Add sysfs RAPL PL1 interface | expand

Commit Message

Sundaresan, Sujaritha Jan. 31, 2023, 6:25 a.m. UTC 
Adding sysfs attribute rapl_pl1_freq_mhz. This shows the RAPL PL1
FREQUENCY LIMIT.

Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  4 ++++
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/gt/intel_rps.c         | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_rps.h         |  1 +
 4 files changed, 38 insertions(+)

Comments

kernel test robot Jan. 31, 2023, 9:21 a.m. UTC | #1 
Hi Sujaritha,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Sujaritha-Sundaresan/drm-i915-gt-Add-sysfs-RAPL-PL1-interface/20230131-152446
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230131062550.11901-1-sujaritha.sundaresan%40intel.com
patch subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Add sysfs RAPL PL1 interface
config: x86_64-rhel-8.3-rust (https://download.01.org/0day-ci/archive/20230131/202301311720.VOyrcus2-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/562c57549ee00ea298f9023380d44526d6d68921
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Sujaritha-Sundaresan/drm-i915-gt-Add-sysfs-RAPL-PL1-interface/20230131-152446
        git checkout 562c57549ee00ea298f9023380d44526d6d68921
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_rps.c:2217:6: warning: variable 'rapl' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
           if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:565:33: note: expanded from macro 'IS_METEORLAKE'
   #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
                                   ^
   drivers/gpu/drm/i915/gt/intel_rps.c:2220:9: note: uninitialized use occurs here
           return rapl;
                  ^~~~
   drivers/gpu/drm/i915/gt/intel_rps.c:2217:2: note: remove the 'if' if its condition is always true
           if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_rps.c:2209:10: note: initialize the variable 'rapl' to silence this warning
           u32 rapl;
                   ^
                    = 0
   1 warning generated.


vim +2217 drivers/gpu/drm/i915/gt/intel_rps.c

  2204	
  2205	u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
  2206	{
  2207		struct drm_i915_private *i915 = rps_to_i915(rps);
  2208		u32 rapl_pl1;
  2209		u32 rapl;
  2210	
  2211		if (IS_METEORLAKE(i915))
  2212			rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_RAPL_PL1_FREQ_LIMIT);
  2213		else if (IS_XEHPSDV(i915))
  2214			rapl_pl1  = intel_uncore_read(rps_to_gt(rps)->uncore, XEHPSDV_RAPL_PL1_FREQ_LIMIT);
  2215	
  2216	
> 2217		if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
  2218			rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
  2219	
  2220		return rapl;
  2221	}
  2222
kernel test robot Jan. 31, 2023, 1:05 p.m. UTC | #2 
Hi Sujaritha,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Sujaritha-Sundaresan/drm-i915-gt-Add-sysfs-RAPL-PL1-interface/20230131-152446
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230131062550.11901-1-sujaritha.sundaresan%40intel.com
patch subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Add sysfs RAPL PL1 interface
config: i386-randconfig-a012-20230130 (https://download.01.org/0day-ci/archive/20230131/202301312135.zxf6axNP-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/562c57549ee00ea298f9023380d44526d6d68921
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Sujaritha-Sundaresan/drm-i915-gt-Add-sysfs-RAPL-PL1-interface/20230131-152446
        git checkout 562c57549ee00ea298f9023380d44526d6d68921
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_rps.c:2217:6: error: variable 'rapl' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
           if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:565:33: note: expanded from macro 'IS_METEORLAKE'
   #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
                                   ^
   drivers/gpu/drm/i915/gt/intel_rps.c:2220:9: note: uninitialized use occurs here
           return rapl;
                  ^~~~
   drivers/gpu/drm/i915/gt/intel_rps.c:2217:2: note: remove the 'if' if its condition is always true
           if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_rps.c:2209:10: note: initialize the variable 'rapl' to silence this warning
           u32 rapl;
                   ^
                    = 0
   1 error generated.


vim +2217 drivers/gpu/drm/i915/gt/intel_rps.c

  2204	
  2205	u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
  2206	{
  2207		struct drm_i915_private *i915 = rps_to_i915(rps);
  2208		u32 rapl_pl1;
  2209		u32 rapl;
  2210	
  2211		if (IS_METEORLAKE(i915))
  2212			rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_RAPL_PL1_FREQ_LIMIT);
  2213		else if (IS_XEHPSDV(i915))
  2214			rapl_pl1  = intel_uncore_read(rps_to_gt(rps)->uncore, XEHPSDV_RAPL_PL1_FREQ_LIMIT);
  2215	
  2216	
> 2217		if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
  2218			rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
  2219	
  2220		return rapl;
  2221	}
  2222
Dixit, Ashutosh Jan. 31, 2023, 8:33 p.m. UTC | #3 
On Mon, 30 Jan 2023 22:25:50 -0800, Sujaritha Sundaresan wrote:
>

Hi Suja,

> Adding sysfs attribute rapl_pl1_freq_mhz. This shows the RAPL PL1
> FREQUENCY LIMIT.

For MTL do we know if this RAPL PL1 freq limit is for just the GPU or the
SOC (CPU + GPU)?

>
> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  4 ++++
>  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_rps.c         | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_rps.h         |  1 +
>  4 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 7fa18a3b3957..1c78fc89a37a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1656,6 +1656,10 @@
>  #define GT0_PACKAGE_POWER_SKU_UNIT		_MMIO(0x250068)
>  #define GT0_PLATFORM_ENERGY_STATUS		_MMIO(0x25006c)
>
> +#define XEHPSDV_RAPL_PL1_FREQ_LIMIT		_MMIO(0x250070)
> +#define MTL_RAPL_PL1_FREQ_LIMIT		_MMIO(0x281070)
> +#define   RAPL_PL1_FREQ_LIMIT_MASK		REG_GENMASK(15, 0)
> +
>  /*
>   * Standalone Media's non-engine GT registers are located at their regular GT
>   * offsets plus 0x380000.  This extra offset is stored inside the intel_uncore
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 28f27091cd3b..0b52962e2856 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -451,6 +451,16 @@ static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
>	return sysfs_emit(buff, "%u\n", preq);
>  }
>
> +static ssize_t rapl_pl1_freq_mhz_show(struct kobject *kobj,
> +				      struct kobj_attribute *attr,
> +				      char *buff)
> +{
> +	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
> +	u32 rapl_pl1 = intel_rps_read_rapl_pl1(&gt->rps);
> +
> +	return sysfs_emit(buff, "%u\n", rapl_pl1);
> +}
> +
>  struct intel_gt_bool_throttle_attr {
>	struct attribute attr;
>	ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
> @@ -480,6 +490,7 @@ struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
>  }
>
>  INTEL_GT_ATTR_RO(punit_req_freq_mhz);
> +INTEL_GT_ATTR_RO(rapl_pl1_freq_mhz);
>  static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
>  static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
>  static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
> @@ -744,6 +755,10 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
>	if (ret)
>		gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
>
> +	ret = sysfs_create_file(kobj, &attr_rapl_pl1_freq_mhz.attr);
> +	if (ret)
> +		gt_warn(gt, "failed to create rapl_pl1_freq_mhz sysfs (%pe)", ERR_PTR(ret));
> +

As I said previously we should create the rapl_pl1_freq_mhz file only on
platforms on which it is is available. So let's put the above code block
inside the if () below:

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70) || IS_XEHPSDV(gt->i915)) {
		ret = sysfs_create_file(kobj, &attr_rapl_pl1_freq_mhz.attr);
		if (ret)
			gt_warn(gt, "failed to create rapl_pl1_freq_mhz sysfs (%pe)", ERR_PTR(ret));
	}

Where MTL graphics version is 12.70 so I am assuming this will be availble
for all later products too and it will help us to not modify the code for
each individual product (unless we have to).

>	if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
>		ret = sysfs_create_files(kobj, throttle_reason_attrs);
>		if (ret)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index f5d7b5126433..f66d6f47f2cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2202,6 +2202,24 @@ u32 intel_rps_get_max_frequency(struct intel_rps *rps)
>		return intel_gpu_freq(rps, rps->max_freq_softlimit);
>  }
>
> +u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
> +{
> +	struct drm_i915_private *i915 = rps_to_i915(rps);
> +	u32 rapl_pl1;
> +	u32 rapl;
> +
> +	if (IS_METEORLAKE(i915))
> +		rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_RAPL_PL1_FREQ_LIMIT);
> +	else if (IS_XEHPSDV(i915))
> +		rapl_pl1  = intel_uncore_read(rps_to_gt(rps)->uncore, XEHPSDV_RAPL_PL1_FREQ_LIMIT);
> +
> +
> +	if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
> +		rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
> +
> +	return rapl;
> +}

This should be something like this:

u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
{
	struct drm_i915_private *i915 = rps_to_i915(rps);
	i915_reg_t rgadr = INVALID_MMIO_REG;
	u32 rapl_pl1, rapl;

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
		rgadr = MTL_RAPL_PL1_FREQ_LIMIT;
	else if (IS_XEHPSDV(i915))
		rgadr = XEHPSDV_RAPL_PL1_FREQ_LIMIT;

	rapl_pl1 = rps_read_mmio(gt, rgadr);
	rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);

	return rapl;
}

rps_read_mmio is needed to take the runtime PM wakeref, we cannot use
intel_uncore_read directly. Note also that we've already ensured that
rapl_pl1_freq_mhz file is only available for XEHPSDV and >= 12.70.

Thanks.
--
Ashutosh

> +
>  /**
>   * intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
>   * @rps: the intel_rps structure
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> index c622962c6bef..c37d297c9d82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -51,6 +51,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
>  u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
>  u32 intel_rps_read_punit_req(struct intel_rps *rps);
>  u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
> +u32 intel_rps_read_rapl_pl1(struct intel_rps *rps);
>  u32 intel_rps_read_rpstat(struct intel_rps *rps);
>  u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
>  void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7fa18a3b3957..1c78fc89a37a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1656,6 +1656,10 @@ 
 #define GT0_PACKAGE_POWER_SKU_UNIT		_MMIO(0x250068)
 #define GT0_PLATFORM_ENERGY_STATUS		_MMIO(0x25006c)
 
+#define XEHPSDV_RAPL_PL1_FREQ_LIMIT		_MMIO(0x250070)
+#define MTL_RAPL_PL1_FREQ_LIMIT		_MMIO(0x281070)
+#define   RAPL_PL1_FREQ_LIMIT_MASK		REG_GENMASK(15, 0)
+
 /*
  * Standalone Media's non-engine GT registers are located at their regular GT
  * offsets plus 0x380000.  This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 28f27091cd3b..0b52962e2856 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -451,6 +451,16 @@  static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
 	return sysfs_emit(buff, "%u\n", preq);
 }
 
+static ssize_t rapl_pl1_freq_mhz_show(struct kobject *kobj,
+				      struct kobj_attribute *attr,
+				      char *buff)
+{
+	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
+	u32 rapl_pl1 = intel_rps_read_rapl_pl1(&gt->rps);
+
+	return sysfs_emit(buff, "%u\n", rapl_pl1);
+}
+
 struct intel_gt_bool_throttle_attr {
 	struct attribute attr;
 	ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
@@ -480,6 +490,7 @@  struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
 }
 
 INTEL_GT_ATTR_RO(punit_req_freq_mhz);
+INTEL_GT_ATTR_RO(rapl_pl1_freq_mhz);
 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
@@ -744,6 +755,10 @@  void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
 	if (ret)
 		gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
 
+	ret = sysfs_create_file(kobj, &attr_rapl_pl1_freq_mhz.attr);
+	if (ret)
+		gt_warn(gt, "failed to create rapl_pl1_freq_mhz sysfs (%pe)", ERR_PTR(ret));
+
 	if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
 		ret = sysfs_create_files(kobj, throttle_reason_attrs);
 		if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index f5d7b5126433..f66d6f47f2cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2202,6 +2202,24 @@  u32 intel_rps_get_max_frequency(struct intel_rps *rps)
 		return intel_gpu_freq(rps, rps->max_freq_softlimit);
 }
 
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps)
+{
+	struct drm_i915_private *i915 = rps_to_i915(rps);
+	u32 rapl_pl1;
+	u32 rapl;
+
+	if (IS_METEORLAKE(i915))
+		rapl_pl1 = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_RAPL_PL1_FREQ_LIMIT);
+	else if (IS_XEHPSDV(i915))
+		rapl_pl1  = intel_uncore_read(rps_to_gt(rps)->uncore, XEHPSDV_RAPL_PL1_FREQ_LIMIT);
+
+
+	if (IS_METEORLAKE(i915) || IS_XEHPSDV(i915))
+		rapl = REG_FIELD_GET(RAPL_PL1_FREQ_LIMIT_MASK, rapl_pl1);
+
+	return rapl;
+}
+
 /**
  * intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
  * @rps: the intel_rps structure
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index c622962c6bef..c37d297c9d82 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -51,6 +51,7 @@  u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
 u32 intel_rps_read_punit_req(struct intel_rps *rps);
 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rapl_pl1(struct intel_rps *rps);
 u32 intel_rps_read_rpstat(struct intel_rps *rps);
 u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
 void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);