Message ID | 1675330898-563-5-git-send-email-manikanta.guntupalli@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
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Added Standard mode and SMBus support.
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On Thu, Feb 02, 2023 at 03:11:33PM +0530, Manikanta Guntupalli wrote: > From: Raviteja Narayanam <raviteja.narayanam@xilinx.com> > > If the tx_half_empty interrupt comes first instead of tx_empty, > STOP bit is generated even before all the bytes are transmitted > out on the bus. > STOP bit should be sent only after all the bytes in the FIFO are > transmitted out of the FIFO. So wait until FIFO is empty before sending > the STOP bit. > > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> > Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> > Acked-by: Michal Simek <michal.simek@amd.com> Applied to for-next, thanks!
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index edc64b79e293..57084696429c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) data |= XIIC_TX_DYN_STOP_MASK; } else { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &