[05/18] target/riscv: Coding style fixes in csr.c

Message ID	20230213180215.1524938-6-bmeng@tinylab.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Bin Meng <bmeng@tinylab.org> To: qemu-devel@nongnu.org Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liweiwei@iscas.ac.cn>, qemu-riscv@nongnu.org Subject: [PATCH 05/18] target/riscv: Coding style fixes in csr.c Date: Tue, 14 Feb 2023 02:02:01 +0800 Message-Id: <20230213180215.1524938-6-bmeng@tinylab.org> In-Reply-To: <20230213180215.1524938-1-bmeng@tinylab.org> References: <20230213180215.1524938-1-bmeng@tinylab.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 Received-SPF: pass client-ip=43.155.65.254; envelope-from=bmeng@tinylab.org; helo=bg4.exmail.qq.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	target/riscv: Various fixes to gdbstub and CSR access \| expand [00/18] target/riscv: Various fixes to gdbstub and CSR access [01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR [02/18] target/riscv: Correct the priority policy of riscv_csrrw_check() [03/18] target/riscv: gdbstub: Minor change for better readability [04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled [05/18] target/riscv: Coding style fixes in csr.c [06/18] target/riscv: Use 'bool' type for read_only [07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit [08/18] target/riscv: Simplify getting RISCVCPU pointer from env [09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 [10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() [11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml [12/18] target/riscv: Allow debugger to access user timer and counter CSRs [13/18] target/riscv: Allow debugger to access seed CSR [14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs [15/18] target/riscv: Allow debugger to access sstc CSRs [16/18] target/riscv: Drop priv level check in mseccfg predicate() [17/18] target/riscv: Group all predicate() routines together [18/18] target/riscv: Move configuration check to envcfg CSRs predicate()

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20230213180215.1524938-6-bmeng@tinylab.org (mailing list archive)

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Headers

From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
 Bin Meng <bin.meng@windriver.com>,
 Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
 Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liweiwei@iscas.ac.cn>,
 qemu-riscv@nongnu.org
Subject: [PATCH 05/18] target/riscv: Coding style fixes in csr.c
Date: Tue, 14 Feb 2023 02:02:01 +0800
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Series

target/riscv: Various fixes to gdbstub and CSR access | expand

Commit Message

Bin Meng Feb. 13, 2023, 6:02 p.m. UTC

Fix various places that violate QEMU coding style:

- correct multi-line comment format
- indent to opening parenthesis

Signed-off-by: Bin Meng <bmeng@tinylab.org>
---

 target/riscv/csr.c | 62 ++++++++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 30 deletions(-)

Comments

Weiwei Li Feb. 14, 2023, 8:48 a.m. UTC | #1

On 2023/2/14 02:02, Bin Meng wrote:
> Fix various places that violate QEMU coding style:
>
> - correct multi-line comment format
> - indent to opening parenthesis
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,
Weiwei Li
> ---
>
>   target/riscv/csr.c | 62 ++++++++++++++++++++++++----------------------
>   1 file changed, 32 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c2dd9d5af0..cc74819759 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
>   }
>   
>   static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                     target_ulong *val)
>   {
>       *val = env->vstimecmp;
>   
> @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                      target_ulong *val)
>   {
>       *val = env->vstimecmp >> 32;
>   
> @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                      target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                       target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                     target_ulong *val)
>   {
>       if (riscv_cpu_virt_enabled(env)) {
>           *val = env->vstimecmp >> 32;
> @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                     target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                      target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>   
>       /* 'E' excludes all other extensions */
>       if (val & RVE) {
> -        /* when we support 'E' we can do "val = RVE;" however
> +        /*
> +         * when we support 'E' we can do "val = RVE;" however
>            * for now we just drop writes if 'E' is present.
>            */
>           return RISCV_EXCP_NONE;
> @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>           val &= ~RVD;
>       }
>   
> -    /* Suppress 'C' if next instruction is not aligned
> +    /*
> +     * Suppress 'C' if next instruction is not aligned
>        * TODO: this should check next_pc
>        */
>       if ((val & RVC) && (GETPC() & ~3) != 0) {
> @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_mepc(CPURISCVState *env, int csrno,
> -                                     target_ulong *val)
> +                                target_ulong *val)
>   {
>       *val = env->mepc;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_mepc(CPURISCVState *env, int csrno,
> -                                     target_ulong val)
> +                                 target_ulong val)
>   {
>       env->mepc = val;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException read_mcause(CPURISCVState *env, int csrno,
> -                                     target_ulong *val)
> +                                  target_ulong *val)
>   {
>       *val = env->mcause;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_mcause(CPURISCVState *env, int csrno,
> -                                     target_ulong val)
> +                                   target_ulong val)
>   {
>       env->mcause = val;
>       return RISCV_EXCP_NONE;
> @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
>   
>   /* Execution environment configuration setup */
>   static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       *val = env->menvcfg;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>   
> @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                    target_ulong *val)
>   {
>       *val = env->menvcfg >> 32;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                     target_ulong val)
>   {
>       uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
>       uint64_t valh = (uint64_t)val << 32;
> @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
>       RISCVException ret;
> @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
>       RISCVException ret;
> @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                    target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                     target_ulong val)
>   {
>       uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
>       uint64_t valh = (uint64_t)val << 32;
> @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                         target_ulong new_val)
>   {
>       return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
>   
>   static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
> -                                      target_ulong *val)
> +                                     target_ulong *val)
>   {
>       *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
>   
> @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                       target_ulong new_val)
>   {
>       uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>   
> @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                          target_ulong new_val)
>   {
>       return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                         target_ulong new_val)
>   {
>       return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
> -                                       target_ulong new_val)
> +                                          target_ulong new_val)
>   {
>       return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
> -                         target_ulong val)
> +                                    target_ulong val)
>   {
>       mseccfg_csr_write(env, val);
>       return RISCV_EXCP_NONE;

LIU Zhiwei Feb. 17, 2023, 2:24 a.m. UTC | #2

On 2023/2/14 2:02, Bin Meng wrote:
> Fix various places that violate QEMU coding style:
>
> - correct multi-line comment format
> - indent to opening parenthesis
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
>   target/riscv/csr.c | 62 ++++++++++++++++++++++++----------------------
>   1 file changed, 32 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c2dd9d5af0..cc74819759 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
>   }
>   
>   static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                     target_ulong *val)
>   {
>       *val = env->vstimecmp;
>   
> @@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                      target_ulong *val)
>   {
>       *val = env->vstimecmp >> 32;
>   
> @@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                      target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                       target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong *val)
> +                                     target_ulong *val)
>   {
>       if (riscv_cpu_virt_enabled(env)) {
>           *val = env->vstimecmp >> 32;
> @@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                     target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> -                                    target_ulong val)
> +                                      target_ulong val)
>   {
>       RISCVCPU *cpu = env_archcpu(env);
>   
> @@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>   
>       /* 'E' excludes all other extensions */
>       if (val & RVE) {
> -        /* when we support 'E' we can do "val = RVE;" however
> +        /*
> +         * when we support 'E' we can do "val = RVE;" however
>            * for now we just drop writes if 'E' is present.
>            */
>           return RISCV_EXCP_NONE;
> @@ -1364,7 +1365,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>           val &= ~RVD;
>       }
>   
> -    /* Suppress 'C' if next instruction is not aligned
> +    /*
> +     * Suppress 'C' if next instruction is not aligned
>        * TODO: this should check next_pc
>        */
>       if ((val & RVC) && (GETPC() & ~3) != 0) {
> @@ -1833,28 +1835,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_mepc(CPURISCVState *env, int csrno,
> -                                     target_ulong *val)
> +                                target_ulong *val)
>   {
>       *val = env->mepc;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_mepc(CPURISCVState *env, int csrno,
> -                                     target_ulong val)
> +                                 target_ulong val)
>   {
>       env->mepc = val;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException read_mcause(CPURISCVState *env, int csrno,
> -                                     target_ulong *val)
> +                                  target_ulong *val)
>   {
>       *val = env->mcause;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_mcause(CPURISCVState *env, int csrno,
> -                                     target_ulong val)
> +                                   target_ulong val)
>   {
>       env->mcause = val;
>       return RISCV_EXCP_NONE;
> @@ -1876,14 +1878,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
>   
>   /* Execution environment configuration setup */
>   static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       *val = env->menvcfg;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>   
> @@ -1896,14 +1898,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                    target_ulong *val)
>   {
>       *val = env->menvcfg >> 32;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                     target_ulong val)
>   {
>       uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
>       uint64_t valh = (uint64_t)val << 32;
> @@ -1914,7 +1916,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1928,7 +1930,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
>       RISCVException ret;
> @@ -1943,7 +1945,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                   target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1957,7 +1959,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                    target_ulong val)
>   {
>       uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
>       RISCVException ret;
> @@ -1977,7 +1979,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> -                                 target_ulong *val)
> +                                    target_ulong *val)
>   {
>       RISCVException ret;
>   
> @@ -1991,7 +1993,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> -                                  target_ulong val)
> +                                     target_ulong val)
>   {
>       uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
>       uint64_t valh = (uint64_t)val << 32;
> @@ -2034,13 +2036,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                         target_ulong new_val)
>   {
>       return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
>   
>   static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
> -                                      target_ulong *val)
> +                                     target_ulong *val)
>   {
>       *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
>   
> @@ -2061,7 +2063,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                       target_ulong new_val)
>   {
>       uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>   
> @@ -2069,7 +2071,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                          target_ulong new_val)
>   {
>       return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -2106,7 +2108,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
> -                                      target_ulong new_val)
> +                                         target_ulong new_val)
>   {
>       return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -2145,7 +2147,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
> -                                       target_ulong new_val)
> +                                          target_ulong new_val)
>   {
>       return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
>   }
> @@ -3338,7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
>   }
>   
>   static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
> -                         target_ulong val)
> +                                    target_ulong val)

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>   {
>       mseccfg_csr_write(env, val);
>       return RISCV_EXCP_NONE;

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c2dd9d5af0..cc74819759 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -963,7 +963,7 @@  static RISCVException sstc_32(CPURISCVState *env, int csrno)
 }
 
 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
-                                    target_ulong *val)
+                                     target_ulong *val)
 {
     *val = env->vstimecmp;
 
@@ -971,7 +971,7 @@  static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
-                                    target_ulong *val)
+                                      target_ulong *val)
 {
     *val = env->vstimecmp >> 32;
 
@@ -979,7 +979,7 @@  static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
-                                    target_ulong val)
+                                      target_ulong val)
 {
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -996,7 +996,7 @@  static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
-                                    target_ulong val)
+                                       target_ulong val)
 {
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -1020,7 +1020,7 @@  static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
-                                    target_ulong *val)
+                                     target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
         *val = env->vstimecmp >> 32;
@@ -1032,7 +1032,7 @@  static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
-                                    target_ulong val)
+                                     target_ulong val)
 {
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -1055,7 +1055,7 @@  static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
-                                    target_ulong val)
+                                      target_ulong val)
 {
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -1342,7 +1342,8 @@  static RISCVException write_misa(CPURISCVState *env, int csrno,
 
     /* 'E' excludes all other extensions */
     if (val & RVE) {
-        /* when we support 'E' we can do "val = RVE;" however
+        /*
+         * when we support 'E' we can do "val = RVE;" however
          * for now we just drop writes if 'E' is present.
          */
         return RISCV_EXCP_NONE;
@@ -1364,7 +1365,8 @@  static RISCVException write_misa(CPURISCVState *env, int csrno,
         val &= ~RVD;
     }
 
-    /* Suppress 'C' if next instruction is not aligned
+    /*
+     * Suppress 'C' if next instruction is not aligned
      * TODO: this should check next_pc
      */
     if ((val & RVC) && (GETPC() & ~3) != 0) {
@@ -1833,28 +1835,28 @@  static RISCVException write_mscratch(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_mepc(CPURISCVState *env, int csrno,
-                                     target_ulong *val)
+                                target_ulong *val)
 {
     *val = env->mepc;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_mepc(CPURISCVState *env, int csrno,
-                                     target_ulong val)
+                                 target_ulong val)
 {
     env->mepc = val;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_mcause(CPURISCVState *env, int csrno,
-                                     target_ulong *val)
+                                  target_ulong *val)
 {
     *val = env->mcause;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_mcause(CPURISCVState *env, int csrno,
-                                     target_ulong val)
+                                   target_ulong val)
 {
     env->mcause = val;
     return RISCV_EXCP_NONE;
@@ -1876,14 +1878,14 @@  static RISCVException write_mtval(CPURISCVState *env, int csrno,
 
 /* Execution environment configuration setup */
 static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+                                   target_ulong *val)
 {
     *val = env->menvcfg;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+                                    target_ulong val)
 {
     uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
 
@@ -1896,14 +1898,14 @@  static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+                                    target_ulong *val)
 {
     *val = env->menvcfg >> 32;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+                                     target_ulong val)
 {
     uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
     uint64_t valh = (uint64_t)val << 32;
@@ -1914,7 +1916,7 @@  static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+                                   target_ulong *val)
 {
     RISCVException ret;
 
@@ -1928,7 +1930,7 @@  static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+                                    target_ulong val)
 {
     uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
     RISCVException ret;
@@ -1943,7 +1945,7 @@  static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+                                   target_ulong *val)
 {
     RISCVException ret;
 
@@ -1957,7 +1959,7 @@  static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+                                    target_ulong val)
 {
     uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
     RISCVException ret;
@@ -1977,7 +1979,7 @@  static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
+                                    target_ulong *val)
 {
     RISCVException ret;
 
@@ -1991,7 +1993,7 @@  static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
-                                  target_ulong val)
+                                     target_ulong val)
 {
     uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
     uint64_t valh = (uint64_t)val << 32;
@@ -2034,13 +2036,13 @@  static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
-                                      target_ulong new_val)
+                                         target_ulong new_val)
 {
     return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
 }
 
 static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
-                                      target_ulong *val)
+                                     target_ulong *val)
 {
     *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
 
@@ -2061,7 +2063,7 @@  static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
-                                      target_ulong new_val)
+                                       target_ulong new_val)
 {
     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
@@ -2069,7 +2071,7 @@  static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
-                                      target_ulong new_val)
+                                          target_ulong new_val)
 {
     return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
 }
@@ -2106,7 +2108,7 @@  static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
-                                      target_ulong new_val)
+                                         target_ulong new_val)
 {
     return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
 }
@@ -2145,7 +2147,7 @@  static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
-                                       target_ulong new_val)
+                                          target_ulong new_val)
 {
     return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
 }
@@ -3338,7 +3340,7 @@  static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
 }
 
 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
-                         target_ulong val)
+                                    target_ulong val)
 {
     mseccfg_csr_write(env, val);
     return RISCV_EXCP_NONE;

[05/18] target/riscv: Coding style fixes in csr.c

Commit Message

Comments

Patch