| Message ID | 20230213180215.1524938-4-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Various fixes to gdbstub and CSR access | expand |
On 2023/2/14 02:01, Bin Meng wrote: > Use a variable 'base_reg' to represent cs->gdb_num_regs so that > the call to ricsv_gen_dynamic_vector_xml() can be placed in one > single line for better readability. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > > target/riscv/gdbstub.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index e57372db38..704f3d6922 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > 32, "riscv-32bit-fpu.xml", 0); > } > if (env->misa_ext & RVV) { > + int base_reg = cs->gdb_num_regs; > gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, > - ricsv_gen_dynamic_vector_xml(cs, > - cs->gdb_num_regs), > + ricsv_gen_dynamic_vector_xml(cs, base_reg), > "riscv-vector.xml", 0); > } > switch (env->misa_mxl_max) {
On 2023/2/14 2:01, Bin Meng wrote: > Use a variable 'base_reg' to represent cs->gdb_num_regs so that > the call to ricsv_gen_dynamic_vector_xml() can be placed in one > single line for better readability. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > target/riscv/gdbstub.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index e57372db38..704f3d6922 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > 32, "riscv-32bit-fpu.xml", 0); > } > if (env->misa_ext & RVV) { > + int base_reg = cs->gdb_num_regs; > gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, > - ricsv_gen_dynamic_vector_xml(cs, > - cs->gdb_num_regs), > + ricsv_gen_dynamic_vector_xml(cs, base_reg), Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > "riscv-vector.xml", 0); > } > switch (env->misa_mxl_max) {
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index e57372db38..704f3d6922 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { + int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, - cs->gdb_num_regs), + ricsv_gen_dynamic_vector_xml(cs, base_reg), "riscv-vector.xml", 0); } switch (env->misa_mxl_max) {
Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng <bmeng@tinylab.org> --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)