| Message ID | 20230216134226.1692107-2-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add the PowerQUICC audio support using the QMC | expand |
On 16/02/2023 14:42, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > --- > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++++++++++++++++++ > include/dt-bindings/soc/fsl,tsa.h | 13 + > 2 files changed, 247 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > new file mode 100644 > index 000000000000..bcd03f89780e > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > @@ -0,0 +1,234 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina <herve.codina@bootlin.com> > + > +description: > + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal serial > + controllers. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#fsl,serial-cells': > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1 > + description: > + TSA consumers that use a phandle to TSA need to pass the serial identifier > + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). > + For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;". > + > +patternProperties: > + '^tdm@[0-1]$': > + description: > + The TDM managed by this controller > + type: object > + > + additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 1 > + description: > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx > + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four pins are used. > + With the 'fsl,common-rxtx-pins' property, two pins are used. > + > + clocks: > + minItems: 2 > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + - description: External clock connected to L1TSYNC pin > + - description: External clock connected to L1TCLK pin Blank line > + clock-names: > + minItems: 2 > + items: > + - const: l1rsync > + - const: l1rclk > + - const: l1tsync > + - const: l1tclk > + > + fsl,diagnostic-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [disabled, echo, internal-loopback, control-loopback] > + default: disabled > + description: | > + The diagnostic mode can be used to diagnose some communication issues. > + It should not be set (or set to 'disabled') when diagnostic is not > + needed. I don't think this is property for DT. Are you going to ship devices to customers with diagnostic mode? As you explained: no, so this can never appear. You might need sysfs/debugfs knob. You already got a comment for this. Your explanation "I plan" is not an explanation why DT is suitable for such property. So let's make it more obvious: drop it. > + Diagnostic mode: > + - disabled: > + Diagnostic disabled (ie. normal operation) > + - echo: > + Automatic echo. Rx data is resent on Tx. > + - internal-loopback: > + The TDM transmitter is connected to the receiver. Data appears > + on Tx pin. > + - control-loopback: > + The TDM transmitter is connected to the receiver. The Tx pin is > + disconnected. > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] maxItems: 1 > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the Rx > + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] maxItems: 1 > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the Tx > + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Data is sent on falling edge of the clock (and received on the rising > + edge). If 'clock-falling-edge' is not present, data is sent on the > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sampled with > + the falling edge. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + patternProperties: > + '^fsl,[rt]x-ts-routes$': > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tuple that indicates the Tx or Rx time-slots routes. > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source (Tx) or destination (Rx) serial interface > + (dt-bindings/soc/fsl,tsa.h defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + else: > + properties: > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + - '#fsl,serial-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/fsl,tsa.h> > + > + tsa@ae0 { > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #fsl,serial-cells = <1>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "l1rsync", "l1rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ No spaces after < and before > > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h > new file mode 100644 > index 000000000000..2cc44e867dbe > --- /dev/null > +++ b/include/dt-bindings/soc/fsl,tsa.h Use same name as binding file. > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H > +#define __DT_BINDINGS_SOC_FSL_TSA_H Best regards, Krzysztof
Hi Krzysztof, On Fri, 17 Feb 2023 10:14:48 +0100 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 16/02/2023 14:42, Herve Codina wrote: > > Add support for the time slot assigner (TSA) > > available in some PowerQUICC SoC such as MPC885 > > or MPC866. > > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > > --- > > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++++++++++++++++++ > > include/dt-bindings/soc/fsl,tsa.h | 13 + > > 2 files changed, 247 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > > create mode 100644 include/dt-bindings/soc/fsl,tsa.h [...] > > + > > +patternProperties: > > + '^tdm@[0-1]$': > > + description: > > + The TDM managed by this controller > > + type: object > > + > > + additionalProperties: false > > + > > + properties: > > + reg: > > + minimum: 0 > > + maximum: 1 > > + description: > > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb [...] > > + > > + fsl,rx-frame-sync-delay-bits: > > + enum: [0, 1, 2, 3] > > maxItems: 1 The property is an enum Why this maxItems value ? If I add the maxItems value, I've got some dt_binding_check errors: /xxxx/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml: patternProperties:^tdm@[0-1]$:properties:fsl,rx-frame-sync-delay-bits: 'enum' should not be valid under {'enum': ['const', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'minimum', 'maximum', 'multipleOf', 'pattern']} hint: Scalar and array keywords cannot be mixed from schema $id: http://devicetree.org/meta-schemas/keywords.yaml# > > > + default: 0 > > + description: | > > + Receive frame sync delay in number of bits. > > + Indicates the delay between the Rx sync and the first bit of the Rx > > + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > > + > > + fsl,tx-frame-sync-delay-bits: > > + enum: [0, 1, 2, 3] > > maxItems: 1 Same question here. Thanks for the review, Hervé
On 17/02/2023 14:50, Herve Codina wrote: > Hi Krzysztof, > > On Fri, 17 Feb 2023 10:14:48 +0100 > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > >> On 16/02/2023 14:42, Herve Codina wrote: >>> Add support for the time slot assigner (TSA) >>> available in some PowerQUICC SoC such as MPC885 >>> or MPC866. >>> >>> Signed-off-by: Herve Codina <herve.codina@bootlin.com> >>> --- >>> .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++++++++++++++++++ >>> include/dt-bindings/soc/fsl,tsa.h | 13 + >>> 2 files changed, 247 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml >>> create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > [...] >>> + >>> +patternProperties: >>> + '^tdm@[0-1]$': >>> + description: >>> + The TDM managed by this controller >>> + type: object >>> + >>> + additionalProperties: false >>> + >>> + properties: >>> + reg: >>> + minimum: 0 >>> + maximum: 1 >>> + description: >>> + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > [...] >>> + >>> + fsl,rx-frame-sync-delay-bits: >>> + enum: [0, 1, 2, 3] >> >> maxItems: 1 > > The property is an enum > Why this maxItems value ? Hm, it's an array, but you are right that enum forces dtschema to interpret it as scalar value, so your code is correct. > > If I add the maxItems value, I've got some dt_binding_check errors: > /xxxx/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml: > patternProperties:^tdm@[0-1]$:properties:fsl,rx-frame-sync-delay-bits: > 'enum' should not be valid under {'enum': ['const', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'minimum', 'maximum', 'multipleOf', 'pattern']} > hint: Scalar and array keywords cannot be mixed > from schema $id: http://devicetree.org/meta-schemas/keywords.yaml# Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml new file mode 100644 index 000000000000..bcd03f89780e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml @@ -0,0 +1,234 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC CPM Time-slot assigner (TSA) controller + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. + Its purpose is to route some TDM time-slots to other internal serial + controllers. + +properties: + compatible: + items: + - enum: + - fsl,mpc885-tsa + - fsl,mpc866-tsa + - const: fsl,cpm1-tsa + + reg: + items: + - description: SI (Serial Interface) register base + - description: SI RAM base + + reg-names: + items: + - const: si_regs + - const: si_ram + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#fsl,serial-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + description: + TSA consumers that use a phandle to TSA need to pass the serial identifier + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). + For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;". + +patternProperties: + '^tdm@[0-1]$': + description: + The TDM managed by this controller + type: object + + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 1 + description: + The TDM number for this TDM, 0 for TDMa and 1 for TDMb + + fsl,common-rxtx-pins: + $ref: /schemas/types.yaml#/definitions/flag + description: + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. + Without the 'fsl,common-rxtx-pins' property, the four pins are used. + With the 'fsl,common-rxtx-pins' property, two pins are used. + + clocks: + minItems: 2 + items: + - description: External clock connected to L1RSYNC pin + - description: External clock connected to L1RCLK pin + - description: External clock connected to L1TSYNC pin + - description: External clock connected to L1TCLK pin + clock-names: + minItems: 2 + items: + - const: l1rsync + - const: l1rclk + - const: l1tsync + - const: l1tclk + + fsl,diagnostic-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [disabled, echo, internal-loopback, control-loopback] + default: disabled + description: | + The diagnostic mode can be used to diagnose some communication issues. + It should not be set (or set to 'disabled') when diagnostic is not + needed. + Diagnostic mode: + - disabled: + Diagnostic disabled (ie. normal operation) + - echo: + Automatic echo. Rx data is resent on Tx. + - internal-loopback: + The TDM transmitter is connected to the receiver. Data appears + on Tx pin. + - control-loopback: + The TDM transmitter is connected to the receiver. The Tx pin is + disconnected. + + fsl,rx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Receive frame sync delay in number of bits. + Indicates the delay between the Rx sync and the first bit of the Rx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,tx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Transmit frame sync delay in number of bits. + Indicates the delay between the Tx sync and the first bit of the Tx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,clock-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Data is sent on falling edge of the clock (and received on the rising + edge). If 'clock-falling-edge' is not present, data is sent on the + rising edge (and received on the falling edge). + + fsl,fsync-rising-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Frame sync pulses are sampled with the rising edge of the channel + clock. If 'fsync-rising-edge' is not present, pulses are sampled with + the falling edge. + + fsl,double-speed-clock: + $ref: /schemas/types.yaml#/definitions/flag + description: + The channel clock is twice the data rate. + + patternProperties: + '^fsl,[rt]x-ts-routes$': + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of tuple that indicates the Tx or Rx time-slots routes. + items: + items: + - description: + The number of time-slots + minimum: 1 + maximum: 64 + - description: | + The source (Tx) or destination (Rx) serial interface + (dt-bindings/soc/fsl,tsa.h defines these values) + - 0: No destination + - 1: SCC2 + - 2: SCC3 + - 3: SCC4 + - 4: SMC1 + - 5: SMC2 + enum: [0, 1, 2, 3, 4, 5] + minItems: 1 + maxItems: 64 + + allOf: + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. + # Else, the 4 clocks must be present. + - if: + required: + - fsl,common-rxtx-pins + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + + required: + - reg + - clocks + - clock-names + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - '#fsl,serial-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/fsl,tsa.h> + + tsa@ae0 { + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; + reg = <0xae0 0x10>, + <0xc00 0x200>; + reg-names = "si_regs", "si_ram"; + + #address-cells = <1>; + #size-cells = <0>; + #fsl,serial-cells = <1>; + + tdm@0 { + /* TDMa */ + reg = <0>; + + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; + clock-names = "l1rsync", "l1rclk"; + + fsl,common-rxtx-pins; + fsl,fsync-rising-edge; + + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ + < 1 0 >, /* TS 26 */ + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ + + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ + < 1 0 >, /* TS 26 */ + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ + }; + }; diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h new file mode 100644 index 000000000000..2cc44e867dbe --- /dev/null +++ b/include/dt-bindings/soc/fsl,tsa.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H +#define __DT_BINDINGS_SOC_FSL_TSA_H + +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ +#define FSL_CPM_TSA_SCC2 1 +#define FSL_CPM_TSA_SCC3 2 +#define FSL_CPM_TSA_SCC4 3 +#define FSL_CPM_TSA_SMC1 4 +#define FSL_CPM_TSA_SMC2 5 + +#endif
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++++++++++++++++++ include/dt-bindings/soc/fsl,tsa.h | 13 + 2 files changed, 247 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml create mode 100644 include/dt-bindings/soc/fsl,tsa.h