| Message ID | 20230211104915.116253-2-arinc.unal@arinc9.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b |
| Headers | show |
| Series | [1/2] mips: dts: align LED node names with dtschema | expand |
On Sat, Feb 11, 2023 at 11:50 AM <arinc9.unal@gmail.com> wrote: > > From: Arınç ÜNAL <arinc.unal@arinc9.com> > > On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is > connected to the second MAC of the SoC as a CPU port. Add the port and set > up the second MAC on the bindings. Revert PHY muxing on GB-PC1. > > There's an external PHY connected to the second MAC of the SoC on GB-PC2, > therefore, disable port@5 for this device. > > Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> > --- > .../boot/dts/ralink/mt7621-gnubee-gb-pc1.dts | 16 +++++----------- > .../boot/dts/ralink/mt7621-gnubee-gb-pc2.dts | 9 ++++++++- > arch/mips/boot/dts/ralink/mt7621.dtsi | 19 ++++++++++++++++++- > 3 files changed, 31 insertions(+), 13 deletions(-) Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Thanks, Sergio Paracuellos
On Sat, Feb 11, 2023 at 01:49:15PM +0300, arinc9.unal@gmail.com wrote: > From: Arınç ÜNAL <arinc.unal@arinc9.com> > > On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is > connected to the second MAC of the SoC as a CPU port. Add the port and set > up the second MAC on the bindings. Revert PHY muxing on GB-PC1. > > There's an external PHY connected to the second MAC of the SoC on GB-PC2, > therefore, disable port@5 for this device. > > Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> > --- > .../boot/dts/ralink/mt7621-gnubee-gb-pc1.dts | 16 +++++----------- > .../boot/dts/ralink/mt7621-gnubee-gb-pc2.dts | 9 ++++++++- > arch/mips/boot/dts/ralink/mt7621.dtsi | 19 ++++++++++++++++++- > 3 files changed, 31 insertions(+), 13 deletions(-) applied to mips-next. Thomas.
diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts index 4314aee97e18..129b6710b699 100644 --- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts @@ -91,22 +91,16 @@ &pcie { status = "okay"; }; -&gmac1 { - status = "okay"; - phy-handle = <ðphy4>; -}; - -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; -}; - &switch0 { ports { port@0 { status = "okay"; label = "ethblack"; }; + + port@4 { + status = "okay"; + label = "ethblue"; + }; }; }; diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts index 3ebbf933f644..f810cd10f4f4 100644 --- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts @@ -112,9 +112,12 @@ &pcie { }; &gmac1 { - status = "okay"; phy-mode = "rgmii-rxid"; phy-handle = <ðphy5>; + + fixed-link { + status = "disabled"; + }; }; &mdio { @@ -134,5 +137,9 @@ port@4 { status = "okay"; label = "ethblue"; }; + + port@5 { + status = "disabled"; + }; }; }; diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index aec85c779359..290d47fbcfbb 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -332,8 +332,13 @@ fixed-link { gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; - status = "disabled"; phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; }; mdio: mdio-bus { @@ -384,6 +389,18 @@ port@4 { label = "swp4"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; ethernet = <&gmac0>;