| Message ID | 20230220021915.9473-1-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mediatek: Add cpufreq nodes for MT8192 | expand |
Il 20/02/23 03:19, Allen-KH Cheng ha scritto: > Add the cpufreq nodes for MT8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > Fix a address warning on dtbs_check > https://patchwork.kernel.org/project/linux-mediatek/patch/1609223471-24325-1-git-send-email-andrew-sh.cheng@mediatek.com/ > [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] > --- > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 424fc89cc6f7..181ec2db7a69 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -55,6 +55,7 @@ cpu0: cpu@0 { > clock-frequency = <1701000000>; > cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 1>; There's a mistake here: this should be <&performance 0>; > capacity-dmips-mhz = <530>; > }; > > @@ -66,6 +67,7 @@ cpu1: cpu@100 { > clock-frequency = <1701000000>; > cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 1>; Same here > capacity-dmips-mhz = <530>; > }; > > @@ -77,6 +79,7 @@ cpu2: cpu@200 { > clock-frequency = <1701000000>; > cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 1>; and here > capacity-dmips-mhz = <530>; > }; > > @@ -88,6 +91,7 @@ cpu3: cpu@300 { > clock-frequency = <1701000000>; > cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; > next-level-cache = <&l2_0>; > + performance-domains = <&performance 1>; ....and here. Regards, Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 424fc89cc6f7..181ec2db7a69 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -55,6 +55,7 @@ cpu0: cpu@0 { clock-frequency = <1701000000>; cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <530>; }; @@ -66,6 +67,7 @@ cpu1: cpu@100 { clock-frequency = <1701000000>; cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <530>; }; @@ -77,6 +79,7 @@ cpu2: cpu@200 { clock-frequency = <1701000000>; cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <530>; }; @@ -88,6 +91,7 @@ cpu3: cpu@300 { clock-frequency = <1701000000>; cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <530>; }; @@ -99,6 +103,7 @@ cpu4: cpu@400 { clock-frequency = <2171000000>; cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -110,6 +115,7 @@ cpu5: cpu@500 { clock-frequency = <2171000000>; cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -121,6 +127,7 @@ cpu6: cpu@600 { clock-frequency = <2171000000>; cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -132,6 +139,7 @@ cpu7: cpu@700 { clock-frequency = <2171000000>; cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -254,6 +262,12 @@ soc { compatible = "simple-bus"; ranges; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>;
Add the cpufreq nodes for MT8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- Fix a address warning on dtbs_check https://patchwork.kernel.org/project/linux-mediatek/patch/1609223471-24325-1-git-send-email-andrew-sh.cheng@mediatek.com/ [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] --- --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)