| Message ID | 20230220061745.1973981-1-ryan_chen@aspeedtech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add ASPEED AST2600 I2Cv2 controller driver | expand |
On 20/02/2023 07:17, Ryan Chen wrote: > This series add AST2600 i2cv2 new register set driver. The i2cv2 new > register set have new clock divider option for more flexiable generation. Typo: flexible > And also have separate i2c master and slave register set for control. Since several of my questions remained unanswered and quite frankly it's fruitless... so let me read the commit msg directly - it's the same device, just with different register layout. Having new compatible makes sense, but this should be part of old binding. Best regards, Krzysztof
Hello Krzysztof, Ryan Chen > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Monday, February 20, 2023 4:30 PM > To: Ryan Chen <ryan_chen@aspeedtech.com>; Rob Herring > <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew > Jeffery <andrew@aj.id.au>; Philipp Zabel <p.zabel@pengutronix.de>; > openbmc@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org; > linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v5 0/2] Add ASPEED AST2600 I2Cv2 controller driver > > > On 20/02/2023 07:17, Ryan Chen wrote: > > This series add AST2600 i2cv2 new register set driver. The i2cv2 new > > register set have new clock divider option for more flexiable generation. > > Typo: flexible Will fix typo. > > > And also have separate i2c master and slave register set for control. > > Since several of my questions remained unanswered and quite frankly it's > fruitless... so let me read the commit msg directly - it's the same device, just > with different register layout. Having new compatible makes sense, but this > should be part of old binding. > Sorry, I am confused, Do you mean I should base on original Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml Add new compatible? Not add another aspeed,i2cv2.yaml. Best regards, Ryan
On 20/02/2023 10:56, Ryan Chen wrote: >> >>> And also have separate i2c master and slave register set for control. >> >> Since several of my questions remained unanswered and quite frankly it's >> fruitless... so let me read the commit msg directly - it's the same device, just >> with different register layout. Having new compatible makes sense, but this >> should be part of old binding. >> > Sorry, I am confused, Do you mean I should base on original Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml > Add new compatible? Not add another aspeed,i2cv2.yaml. Yes. New compatible and new syscon phandle (constrained to specific compatibles in allOf:if:then:) to the old binding. Best regards, Krzysztof
Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Monday, February 20, 2023 6:36 PM > To: Ryan Chen <ryan_chen@aspeedtech.com>; Rob Herring > <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew > Jeffery <andrew@aj.id.au>; Philipp Zabel <p.zabel@pengutronix.de>; > openbmc@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org; > linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v5 0/2] Add ASPEED AST2600 I2Cv2 controller driver > > On 20/02/2023 10:56, Ryan Chen wrote: > >> > >>> And also have separate i2c master and slave register set for control. > >> > >> Since several of my questions remained unanswered and quite frankly > >> it's fruitless... so let me read the commit msg directly - it's the > >> same device, just with different register layout. Having new > >> compatible makes sense, but this should be part of old binding. > >> > > Sorry, I am confused, Do you mean I should base on original > > Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml > > Add new compatible? Not add another aspeed,i2cv2.yaml. > > Yes. New compatible and new syscon phandle (constrained to specific > compatibles in allOf:if:then:) to the old binding. Thank your guidance. The following is my sample modify, if my understand is correct, I will update in patch1 thread discussion. I need add in original aspeed,i2c.yaml not aspeed,i2cv2.yaml allOf: - $ref: /schemas/i2c/i2c-controller.yaml# - if: properties: compatible: contains: const: aspeed,ast2600-i2cv2 then: required: - aspeed,gr -as is. Best regards, Ryan Chen
On 21/02/2023 02:12, Ryan Chen wrote: >> Yes. New compatible and new syscon phandle (constrained to specific >> compatibles in allOf:if:then:) to the old binding. > Thank your guidance. > The following is my sample modify, if my understand is correct, I will update in patch1 thread discussion. > I need add in original aspeed,i2c.yaml not aspeed,i2cv2.yaml > allOf: > - $ref: /schemas/i2c/i2c-controller.yaml# > - if: > properties: > compatible: > contains: > const: aspeed,ast2600-i2cv2 > > then: > required: > - aspeed,gr else: properties: aspeed,gr: false Best regards, Krzysztof
This series add AST2600 i2cv2 new register set driver. The i2cv2 new register set have new clock divider option for more flexiable generation. And also have separate i2c master and slave register set for control. The legacy register layout is mix master/slave register control together. The following is add more detail description about new register layout. And new feature set add for register. -Add new clock divider option for more flexible and accurate clock rate generation -Add tCKHighMin timing to guarantee SCL high pulse width. -Add support dual pool buffer mode, split 32 bytes pool buffer of each device into 2 x 16 bytes for Tx and Rx individually. -Increase DMA buffer size to 4096 bytes and support byte alignment. -Re-define the base address of BUS1 ~ BUS16 and Pool buffer. -Re-define registers for separating master and slave mode control. -Support 4 individual DMA buffers for master Tx and Rx, slave Tx and Rx. And following is new register set for package transfer sequence. -New Master operation mode: S -> Aw -> P S -> Aw -> TxD -> P S -> Ar -> RxD -> P S -> Aw -> RxD -> Sr -> Ar -> TxD -> P -Bus SDA lock auto-release capability for new master DMA command mode. -Bus auto timeout for new master/slave DMA mode. The following is two versus register layout. Old: {I2CD00}: Function Control Register {I2CD04}: Clock and AC Timing Control Register {I2CD08}: Clock and AC Timing Control Register {I2CD0C}: Interrupt Control Register {I2CD10}: Interrupt Status Register {I2CD14}: Command/Status Register {I2CD18}: Slave Device Address Register {I2CD1C}: Pool Buffer Control Register {I2CD20}: Transmit/Receive Byte Buffer Register {I2CD24}: DMA Mode Buffer Address Register {I2CD28}: DMA Transfer Length Register {I2CD2C}: Original DMA Mode Buffer Address Setting {I2CD30}: Original DMA Transfer Length Setting and Final Status New Register mode {I2CC00}: Master/Slave Function Control Register {I2CC04}: Master/Slave Clock and AC Timing Control Register {I2CC08}: Master/Slave Transmit/Receive Byte Buffer Register {I2CC0C}: Master/Slave Pool Buffer Control Register {I2CM10}: Master Interrupt Control Register {I2CM14}: Master Interrupt Status Register {I2CM18}: Master Command/Status Register {I2CM1C}: Master DMA Buffer Length Register {I2CS20}: Slave~ Interrupt Control Register {I2CS24}: Slave~ Interrupt Status Register {I2CS28}: Slave~ Command/Status Register {I2CS2C}: Slave~ DMA Buffer Length Register {I2CM30}: Master DMA Mode Tx Buffer Base Address {I2CM34}: Master DMA Mode Rx Buffer Base Address {I2CS38}: Slave~ DMA Mode Tx Buffer Base Address {I2CS3C}: Slave~ DMA Mode Rx Buffer Base Address {I2CS40}: Slave Device Address Register {I2CM48}: Master DMA Length Status Register {I2CS4C}: Slave DMA Length Status Register {I2CC50}: Current DMA Operating Address Status {I2CC54}: Current DMA Operating Length Status v5: -remove ast2600-i2c-global.yaml, i2c-ast2600-global.c. -i2c-ast2600.c -remove legacy clock divide, all go for new clock divide. -remove duplicated read isr. -remove no used driver match -fix probe return for each labels return. -global use mfd driver, driver use phandle to regmap read/write. -rename aspeed,i2c-ast2600.yaml to aspeed,i2cv2.yaml -remove bus-frequency. -add required aspeed,gr -add timeout, byte-mode, buff-mode properites. v4: -fix i2c-ast2600.c driver buffer mode use single buffer conflit in master slave mode both enable. -fix kmemleak issue when use dma mode. -fix typo aspeed,i2c-ast2600.yaml compatible is "aspeed,ast2600-i2c" -fix typo aspeed,i2c-ast2600.ymal to aspeed,i2c-ast2600.yaml v3: -fix i2c global clock divide default value. -remove i2c slave no used dev_dbg info. v2: -add i2c global ymal file commit. -rename file name from new to ast2600. aspeed-i2c-new-global.c -> i2c-ast2600-global.c aspeed-i2c-new-global.h -> i2c-ast2600-global.h i2c-new-aspeed.c -> i2c-ast2600.c -rename all driver function name to ast2600. Ryan Chen (2): dt-bindings: i2c: Add support for ASPEED i2Cv2 i2c: aspeed: support ast2600 i2cv2 new register mode driver .../devicetree/bindings/i2c/aspeed,i2cv2.yaml | 83 + MAINTAINERS | 9 + drivers/i2c/busses/Kconfig | 11 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-ast2600.c | 1703 +++++++++++++++++ 5 files changed, 1807 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/aspeed,i2cv2.yaml create mode 100644 drivers/i2c/busses/i2c-ast2600.c