| Message ID | 20230223180531.15148-1-enachman@marvell.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: dwc: Add support for Marvell AC5 SoC | expand |
On Thu, Feb 23, 2023 at 08:05:24PM +0200, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add support for AC5 SoC with MSI and in message emulated legacy mode. > There are differences in the registers addresses, blocks, DDR location > for coherent DMA allocation and additional implementation specific registers. > In addition, support cases of older Designware IP (Armada 7020) which supports > above 4GB PCIe physical memory window by use of device tree. > ... > Elad Nachman (4): > dt-bindings: PCI: dwc: add DMA, region mask bits > PCI: dwc: support AC5 Legacy PCIe interrupts > PCI: dwc: Introduce Configurable DMA mask > PCI: dwc: Introduce region limit from DT > > Raz Adashi (1): > PCI: armada8k: Add AC5 SoC support > > Vadym Kochan (1): > dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC > > Yuval Shaia (1): > PCI: armada8k: Add MSI support for AC5 SoC Capitalize subject consistently. Use consistent driver tags. Use parallel sentence structure. s/add DMA/Add DMA/ s/PCI: dwc: support/PCI: armada8k: Support/ (this particular patch only affects armada8k, so don't label it "dwc") s/support/Support/ s/Configurable/configurable/ s/Add MSI support for AC5 SoC/Add AC5 MSI support/ (parallel to "Add AC5 SoC support") The PCIe spec doesn't really use "legacy" when defining the interrupt model. I think you're referring to INTx, which it *does* use and is more specific. If so, please say "INTx interrupts" instead of "legacy PCIe interrupts".
From: Elad Nachman <enachman@marvell.com> Add support for AC5 SoC with MSI and in message emulated legacy mode. There are differences in the registers addresses, blocks, DDR location for coherent DMA allocation and additional implementation specific registers. In addition, support cases of older Designware IP (Armada 7020) which supports above 4GB PCIe physical memory window by use of device tree. v3: 1) Add dt bindings for DMA and region mask bits 2) Support AC5 Legacy PCIe interrupts 3) Introduce Configurable DMA mask 4) Introduce region limit from DT v2: 1) add patch with adding compatible string for dt-bindings description 2) fix W1 warnings which caused by unused leftover code 3) Use one xlate function to translate ac5 dbi access. Also add mode description in comments about this translation. 4) Use correct name of Raz 5) Use matching data to pass the SoC specific params (type & ops) Elad Nachman (4): dt-bindings: PCI: dwc: add DMA, region mask bits PCI: dwc: support AC5 Legacy PCIe interrupts PCI: dwc: Introduce Configurable DMA mask PCI: dwc: Introduce region limit from DT Raz Adashi (1): PCI: armada8k: Add AC5 SoC support Vadym Kochan (1): dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC Yuval Shaia (1): PCI: armada8k: Add MSI support for AC5 SoC .../devicetree/bindings/pci/pci-armada8k.txt | 4 +- .../bindings/pci/snps,dw-pcie-common.yaml | 10 + drivers/pci/controller/dwc/pcie-armada8k.c | 184 +++++++++++++++--- .../pci/controller/dwc/pcie-designware-host.c | 23 ++- drivers/pci/controller/dwc/pcie-designware.c | 13 +- 5 files changed, 197 insertions(+), 37 deletions(-)