| Message ID | 20230224120738.329416-2-nava.kishore.manne@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Adds status interface for zynqmp-fpga | expand |
On 2023-02-24 at 17:37:37 +0530, Nava kishore Manne wrote: > Adds PM API for performing Programmable Logic(PL) configuration > register readback. It provides an interface to the firmware(pmufw) > to readback the FPGA configuration register. > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> Acked-by: Xu Yilun <yilun.xu@intel.com> > --- > changes for v2: > - None. > > Changes for v3: > - Updated API and config reg read-back handling logic > - Updated the commit msg to align with the changes. > > Changes for v4: > - Fixed some minor coding issues. No functional changes. > - Updated Return value comments as suggested by Xu Yilun. > > Changes for v5: > - Fixed some minor coding issues as suggested by Xu Yilun. > No functional changes. > > Changes for v6: > - None. > > Changes for v7: > - None. > > drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++ > include/linux/firmware/xlnx-zynqmp.h | 11 ++++++++++ > 2 files changed, 44 insertions(+) > > diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c > index 129f68d7a6f5..3d8cc6795b43 100644 > --- a/drivers/firmware/xilinx/zynqmp.c > +++ b/drivers/firmware/xilinx/zynqmp.c > @@ -948,6 +948,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) > } > EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); > > +/** > + * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status. > + * @value: Buffer to store FPGA configuration status. > + * > + * This function provides access to the pmufw to get the FPGA configuration > + * status > + * > + * Return: 0 on success, a negative value on error > + */ > +int zynqmp_pm_fpga_get_config_status(u32 *value) > +{ > + u32 ret_payload[PAYLOAD_ARG_CNT]; > + u32 buf, lower_addr, upper_addr; > + int ret; > + > + if (!value) > + return -EINVAL; > + > + lower_addr = lower_32_bits((u64)&buf); > + upper_addr = upper_32_bits((u64)&buf); > + > + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ, > + XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET, > + lower_addr, upper_addr, > + XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG, > + ret_payload); > + > + *value = ret_payload[1]; > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status); > + > /** > * zynqmp_pm_pinctrl_request - Request Pin from firmware > * @pin: Pin number to request > diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h > index b09f443d3ab9..ce37d55ffa44 100644 > --- a/include/linux/firmware/xlnx-zynqmp.h > +++ b/include/linux/firmware/xlnx-zynqmp.h > @@ -71,6 +71,10 @@ > #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U > #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) > > +/* FPGA Status Reg */ > +#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U > +#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U > + > /* > * Node IDs for the Error Events. > */ > @@ -120,6 +124,7 @@ enum pm_api_id { > PM_CLOCK_GETRATE = 42, > PM_CLOCK_SETPARENT = 43, > PM_CLOCK_GETPARENT = 44, > + PM_FPGA_READ = 46, > PM_SECURE_AES = 47, > PM_FEATURE_CHECK = 63, > }; > @@ -515,6 +520,7 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out); > int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_get_status(u32 *value); > +int zynqmp_pm_fpga_get_config_status(u32 *value); > int zynqmp_pm_write_ggs(u32 index, u32 value); > int zynqmp_pm_read_ggs(u32 index, u32 *value); > int zynqmp_pm_write_pggs(u32 index, u32 value); > @@ -721,6 +727,11 @@ static inline int zynqmp_pm_fpga_get_status(u32 *value) > return -ENODEV; > } > > +static inline int zynqmp_pm_fpga_get_config_status(u32 *value) > +{ > + return -ENODEV; > +} > + > static inline int zynqmp_pm_write_ggs(u32 index, u32 value) > { > return -ENODEV; > -- > 2.25.1 >
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 129f68d7a6f5..3d8cc6795b43 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -948,6 +948,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); +/** + * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status. + * @value: Buffer to store FPGA configuration status. + * + * This function provides access to the pmufw to get the FPGA configuration + * status + * + * Return: 0 on success, a negative value on error + */ +int zynqmp_pm_fpga_get_config_status(u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 buf, lower_addr, upper_addr; + int ret; + + if (!value) + return -EINVAL; + + lower_addr = lower_32_bits((u64)&buf); + upper_addr = upper_32_bits((u64)&buf); + + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ, + XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET, + lower_addr, upper_addr, + XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG, + ret_payload); + + *value = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status); + /** * zynqmp_pm_pinctrl_request - Request Pin from firmware * @pin: Pin number to request diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index b09f443d3ab9..ce37d55ffa44 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -71,6 +71,10 @@ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) +/* FPGA Status Reg */ +#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U +#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U + /* * Node IDs for the Error Events. */ @@ -120,6 +124,7 @@ enum pm_api_id { PM_CLOCK_GETRATE = 42, PM_CLOCK_SETPARENT = 43, PM_CLOCK_GETPARENT = 44, + PM_FPGA_READ = 46, PM_SECURE_AES = 47, PM_FEATURE_CHECK = 63, }; @@ -515,6 +520,7 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); +int zynqmp_pm_fpga_get_config_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); int zynqmp_pm_read_ggs(u32 index, u32 *value); int zynqmp_pm_write_pggs(u32 index, u32 value); @@ -721,6 +727,11 @@ static inline int zynqmp_pm_fpga_get_status(u32 *value) return -ENODEV; } +static inline int zynqmp_pm_fpga_get_config_status(u32 *value) +{ + return -ENODEV; +} + static inline int zynqmp_pm_write_ggs(u32 index, u32 value) { return -ENODEV;
Adds PM API for performing Programmable Logic(PL) configuration register readback. It provides an interface to the firmware(pmufw) to readback the FPGA configuration register. Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> --- changes for v2: - None. Changes for v3: - Updated API and config reg read-back handling logic - Updated the commit msg to align with the changes. Changes for v4: - Fixed some minor coding issues. No functional changes. - Updated Return value comments as suggested by Xu Yilun. Changes for v5: - Fixed some minor coding issues as suggested by Xu Yilun. No functional changes. Changes for v6: - None. Changes for v7: - None. drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 11 ++++++++++ 2 files changed, 44 insertions(+)