| Message ID | 20230214093459.3617293-3-arun.r.murthy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DP2.0 SDP CRC16 for 128/132b link layer | expand |
On Tue, 14 Feb 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote: > Enable SDP error detection configuration, this will set CRC16 in > 128b/132b link layer. > For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is > added to enable/disable SDP CRC applicable for DP2.0 only, but the > default value of this bit will enable CRC16 in 128b/132b hence > skipping this write. > Corrective actions on SDP corruption is yet to be defined. > > v2: Moved the CRC enable to link training init(Jani N) > v3: Moved crc enable to ddi pre enable <Jani N> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 254559abedfb..fa995341614d 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2330,6 +2330,18 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > crtc_state->port_clock, > crtc_state->lane_count); > > + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ > + if (intel_dp_is_uhbr(crtc_state)) > + drm_dp_dpcd_writeb(&intel_dp->aux, > + DP_SDP_ERROR_DETECTION_CONFIGURATION, > + DP_SDP_CRC16_128B132B_EN); > + /* > + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not > + * disable SDP CRC. This is applicable for Display version 13. > + * Default value of bit 31 is '0' hence discarding the write > + */ > + /* TODO: Corrective actions on SDP corruption yet to be defined */ > + So yeah, I told you to do this in this function. But look at the surroundings, does it look like a direct drm_dp_dpcd_writeb() call fits here? tgl_ddi_pre_enable_dp() is a function that calls functions, and doesn't bother with any details. No register or DPCD reads or writes. Sure, it's a matter of style, and I hate to feel like I'm pushing you around with this. But the above really needs to be in a separate function when it's done in tgl_ddi_pre_enable_dp(). It'll also help with placing the comments. You can have *one* block comment above the function with all the details, TODO notes and everything, indented at the top level. (Above, the comments are indented as if they were within a {} block.) BR, Jani. > /* > * We only configure what the register value will be here. Actual > * enabling happens during link training farther down.
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 254559abedfb..fa995341614d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2330,6 +2330,18 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state->port_clock, crtc_state->lane_count); + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (intel_dp_is_uhbr(crtc_state)) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_SDP_ERROR_DETECTION_CONFIGURATION, + DP_SDP_CRC16_128B132B_EN); + /* + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not + * disable SDP CRC. This is applicable for Display version 13. + * Default value of bit 31 is '0' hence discarding the write + */ + /* TODO: Corrective actions on SDP corruption yet to be defined */ + /* * We only configure what the register value will be here. Actual * enabling happens during link training farther down.
Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. v2: Moved the CRC enable to link training init(Jani N) v3: Moved crc enable to ddi pre enable <Jani N> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)