[v2,0/2] hw/cxl: Passthrough HDM decoder emulation

Message

Jonathan Cameron Feb. 27, 2023, 3:31 p.m. UTC

v2:
- Rebase and pick up tags.
- State prereq patche sets more clearly.

Mostly sending out again because some of the precursors have been updated
and to fix a typo in a tag given on v1.

Until now, testing using CXL has relied up always using two root ports
below a host bridge, to work around a current assumption in the Linux
kernel support that, in the single root port case, the implementation will
use the allowed passthrough decoder implementation choice. If that choice
is made all accesses are routed from the host bridge to the single
root port that is present. Effectively we have a pass through decoder
(it is called that in the kernel driver).

This patch series implements that functionality and makes it the default
See patch 2 for a discussion of why I think we can make this change
without backwards compatibility issues (basically if it didn't work before
who are we breaking by making it work?)

Whilst this limitation has been known since the initial QEMU patch
postings / kernel CXL region support, Fan Ni ran into it recently reminding
me that we should solve it.

Note that if you enable hdm_for_passthrough and use a configuration that
would otherwise get a passthrough decoder, the linux kernel will currently
fail to set it up correctly.  That's a bug / missing feature in Linux
not an issue with the emulation.

Based on series "[PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream"
Based on series "[PATCH v6 0/8] hw/cxl: RAS error emulation and injection"

Based on: Message-Id: [e-mail]
Based on: Message-Id: [e-mail]

Jonathan Cameron (2):
  hw/pci: Add pcie_count_ds_port() and pcie_find_port_first() helpers
  hw/pxb-cxl: Support passthrough HDM Decoders unless overridden

 hw/cxl/cxl-host.c                   | 31 ++++++++++++--------
 hw/pci-bridge/pci_expander_bridge.c | 44 +++++++++++++++++++++++++----
 hw/pci/pcie_port.c                  | 38 +++++++++++++++++++++++++
 include/hw/cxl/cxl.h                |  1 +
 include/hw/cxl/cxl_component.h      |  1 +
 include/hw/pci/pci_bridge.h         |  1 +
 include/hw/pci/pcie_port.h          |  2 ++
 7 files changed, 101 insertions(+), 17 deletions(-)

Comments

Fan Ni Feb. 27, 2023, 9:44 p.m. UTC | #1

On Mon, Feb 27, 2023 at 03:31:26PM +0000, Jonathan Cameron wrote:

> v2:
> - Rebase and pick up tags.
> - State prereq patche sets more clearly.
> 
> Mostly sending out again because some of the precursors have been updated
> and to fix a typo in a tag given on v1.
> 
> Until now, testing using CXL has relied up always using two root ports
> below a host bridge, to work around a current assumption in the Linux
> kernel support that, in the single root port case, the implementation will
> use the allowed passthrough decoder implementation choice. If that choice
> is made all accesses are routed from the host bridge to the single
> root port that is present. Effectively we have a pass through decoder
> (it is called that in the kernel driver).
> 
> This patch series implements that functionality and makes it the default
> See patch 2 for a discussion of why I think we can make this change
> without backwards compatibility issues (basically if it didn't work before
> who are we breaking by making it work?)
> 
> Whilst this limitation has been known since the initial QEMU patch
> postings / kernel CXL region support, Fan Ni ran into it recently reminding
> me that we should solve it.
> 
> Note that if you enable hdm_for_passthrough and use a configuration that
> would otherwise get a passthrough decoder, the linux kernel will currently
> fail to set it up correctly.  That's a bug / missing feature in Linux
> not an issue with the emulation.
> 
> Based on series "[PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream"
> Based on series "[PATCH v6 0/8] hw/cxl: RAS error emulation and injection"
> 
> Based on: Message-Id: [e-mail]
> Based on: Message-Id: [e-mail]
> 
> Jonathan Cameron (2):
>   hw/pci: Add pcie_count_ds_port() and pcie_find_port_first() helpers
>   hw/pxb-cxl: Support passthrough HDM Decoders unless overridden
> 
>  hw/cxl/cxl-host.c                   | 31 ++++++++++++--------
>  hw/pci-bridge/pci_expander_bridge.c | 44 +++++++++++++++++++++++++----
>  hw/pci/pcie_port.c                  | 38 +++++++++++++++++++++++++
>  include/hw/cxl/cxl.h                |  1 +
>  include/hw/cxl/cxl_component.h      |  1 +
>  include/hw/pci/pci_bridge.h         |  1 +
>  include/hw/pci/pcie_port.h          |  2 ++
>  7 files changed, 101 insertions(+), 17 deletions(-)
> 
> -- 
> 2.37.2
> 
> 

The code looks good for me.

Applied the two patch series mentioned above before applying this patch
series on ToT, it is clean.
Tested to crete region, create namespace and convert to system RAM and
use it with simple command (numactl --membind=1 htop), no issue related
to the patch has been found.

Also tried with the latest volatile patch (Message-ID:
[e-mail]), creating volatile
region and converting to system RAM (automatically) and online and test
it with the same command as for pmem above works fine.


Fan