| Message ID | 20230130100806.1373883-1-chaitanya.kumar.borah@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add new CDCLK step for RPL-U | expand |
On Mon, 30 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote: > A new step of 480MHz has been added on SKUs that have an RPL-U > device id. This particular step is to support 120Hz panels > more efficiently. > > This patchset adds a new table to include this new CDCLK > step. Details can be found in BSpec entry 55409. > > Create a new sub-platform to identify RPL-U which will enable > us to make the differentiation during CDCLK initialization. Thanks, pushed the series to drm-intel-next. BR, Jani. > > Furthermore, we need to make a distinction between ES (Engineering > Sample) and QS (Quality Sample) parts as this change comes only > to QS parts. This version of the patch does not include this change > as we are yet to make a decision if this particular part needs > to be upstreamed.(see comments on revision 2) > > Chaitanya Kumar Borah (2): > drm/i915: Add RPL-U sub platform > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U > > drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > include/drm/i915_pciids.h | 12 ++++++---- > 5 files changed, 44 insertions(+), 4 deletions(-)
On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote: > A new step of 480MHz has been added on SKUs that have an RPL-U > device id. This particular step is to support 120Hz panels > more efficiently. > > This patchset adds a new table to include this new CDCLK > step. Details can be found in BSpec entry 55409. Hi Chaitanya. It looks like we probably need one more change related to the 480MHz rate beyond what was in this series. For platforms that support this rate, we can set voltage level 1 (see bspec 49208) whereas the i915 code at the moment will push it up to voltage level 2 instead. Matt > > Create a new sub-platform to identify RPL-U which will enable > us to make the differentiation during CDCLK initialization. > > Furthermore, we need to make a distinction between ES (Engineering > Sample) and QS (Quality Sample) parts as this change comes only > to QS parts. This version of the patch does not include this change > as we are yet to make a decision if this particular part needs > to be upstreamed.(see comments on revision 2) > > Chaitanya Kumar Borah (2): > drm/i915: Add RPL-U sub platform > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U > > drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > include/drm/i915_pciids.h | 12 ++++++---- > 5 files changed, 44 insertions(+), 4 deletions(-) > > -- > 2.25.1 >
> -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Tuesday, February 28, 2023 6:06 AM > To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> > Cc: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar, > Uma <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; > Srivatsa, Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S > <matthew.s.atwood@intel.com> > Subject: Re: [RFC 0/2] Add new CDCLK step for RPL-U > > On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote: > > A new step of 480MHz has been added on SKUs that have an RPL-U device > > id. This particular step is to support 120Hz panels more efficiently. > > > > This patchset adds a new table to include this new CDCLK step. Details > > can be found in BSpec entry 55409. > > Hi Chaitanya. It looks like we probably need one more change related to the > 480MHz rate beyond what was in this series. For platforms that support this > rate, we can set voltage level 1 (see bspec 49208) whereas the i915 code at > the moment will push it up to voltage level 2 instead. Hello Matt, Thank you for pointing it out. I will have a look and float a patch ASAP. Regards Chaitanya > > > Matt > > > > > Create a new sub-platform to identify RPL-U which will enable us to > > make the differentiation during CDCLK initialization. > > > > Furthermore, we need to make a distinction between ES (Engineering > > Sample) and QS (Quality Sample) parts as this change comes only to QS > > parts. This version of the patch does not include this change as we > > are yet to make a decision if this particular part needs to be > > upstreamed.(see comments on revision 2) > > > > Chaitanya Kumar Borah (2): > > drm/i915: Add RPL-U sub platform > > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U > > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 26 > ++++++++++++++++++++++ > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++ > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > include/drm/i915_pciids.h | 12 ++++++---- > > 5 files changed, 44 insertions(+), 4 deletions(-) > > > > -- > > 2.25.1 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation