[-next,v14,04/19] riscv: Clear vector regfile on bootup

Message ID	20230224170118.16766-5-andy.chiu@sifive.com (mailing list archive)
State	Changes Requested
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Vincent Chen <vincent.chen@sifive.com>, Guo Ren <guoren@kernel.org>, Masahiro Yamada <masahiroy@kernel.org>, Alexandre Ghiti <alexandre.ghiti@canonical.com> Subject: [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Date: Fri, 24 Feb 2023 17:01:03 +0000 Message-Id: <20230224170118.16766-5-andy.chiu@sifive.com> In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v14,00/19] riscv: Add vector ISA support [-next,v14,01/19] riscv: Rename __switch_to_aux -> fpu [-next,v14,02/19] riscv: Extending cpufeature.c to detect V-extension [-next,v14,03/19] riscv: Add new csr defines related to vector extension [-next,v14,04/19] riscv: Clear vector regfile on bootup [-next,v14,05/19] riscv: Disable Vector Instructions for kernel itself [-next,v14,06/19] riscv: Introduce Vector enable/disable helpers [-next,v14,07/19] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v14,08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v14,09/19] riscv: Add task switch support for vector [-next,v14,10/19] riscv: Allocate user's vector context in the first-use trap [-next,v14,11/19] riscv: Add ptrace vector support [-next,v14,12/19] riscv: signal: check fp-reserved words unconditionally [-next,v14,13/19] riscv: signal: Add sigcontext save/restore for vector [-next,v14,14/19] riscv: signal: Report signal frame size to userspace via auxv [-next,v14,15/19] riscv: signal: validate altstack to reflect Vector [-next,v14,16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v14,17/19] riscv: kvm: Add V extension to KVM ISA [-next,v14,18/19] riscv: KVM: Add vector lazy save/restore support [-next,v14,19/19] riscv: Enable Vector code to be built

Message ID

20230224170118.16766-5-andy.chiu@sifive.com (mailing list archive)

State

Changes Requested

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Vincent Chen <vincent.chen@sifive.com>,
	Guo Ren <guoren@kernel.org>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Alexandre Ghiti <alexandre.ghiti@canonical.com>
Subject: [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup
Date: Fri, 24 Feb 2023 17:01:03 +0000
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

riscv: Add vector ISA support | expand

Commit Message

Andy Chiu Feb. 24, 2023, 5:01 p.m. UTC

From: Greentime Hu <greentime.hu@sifive.com>

clear vector registers on boot if kernel supports V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
[vineetg: broke this out to a seperate patch]
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

Comments

Conor Dooley Feb. 28, 2023, 10:17 p.m. UTC | #1

On Fri, Feb 24, 2023 at 05:01:03PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> clear vector registers on boot if kernel supports V.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: broke this out to a seperate patch]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..3fd6a4bd9c3e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -392,7 +392,7 @@  ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	beqz	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done_fpu
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@  ENTRY(reset_regs)
 	fmv.s.x	f31, zero
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
+.Lreset_regs_done_fpu:
 #endif /* CONFIG_FPU */
-.Lreset_regs_done:
+
+#ifdef CONFIG_RISCV_ISA_V
+	csrr	t0, CSR_MISA
+	li	t1, COMPAT_HWCAP_ISA_V
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done_vector
+
+	/*
+	 * Clear vector registers and reset vcsr
+	 * VLMAX has a defined value, VLEN is a constant,
+	 * and this form of vsetvli is defined to set vl to VLMAX.
+	 */
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	csrs	CSR_VCSR, x0
+	vsetvli t1, x0, e8, m8, ta, ma
+	vmv.v.i v0, 0
+	vmv.v.i v8, 0
+	vmv.v.i v16, 0
+	vmv.v.i v24, 0
+	/* note that the caller must clear SR_VS */
+.Lreset_regs_done_vector:
+#endif /* CONFIG_RISCV_ISA_V */
 	ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */

[-next,v14,04/19] riscv: Clear vector regfile on bootup

Commit Message

Comments

Patch