diff mbox series

spi: spi-sn-f-ospi: fix white spaces and improve code formatting

Message ID 20230223102918.985376-1-d-gole@ti.com (mailing list archive)
State New, archived
Headers show
Series spi: spi-sn-f-ospi: fix white spaces and improve code formatting | expand

Commit Message

Dhruva Gole Feb. 23, 2023, 10:29 a.m. UTC 
Fixes: 1b74dd64c861 ("spi: Add Socionext F_OSPI SPI flash controller driver")

Allignment issues in all the macro definitions of this driver have been
fixed for better asthetics

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/spi/spi-sn-f-ospi.c | 170 ++++++++++++++++++------------------
 1 file changed, 85 insertions(+), 85 deletions(-)

Comments

Mark Brown Feb. 27, 2023, 2:09 p.m. UTC | #1 
On Thu, Feb 23, 2023 at 03:59:18PM +0530, Dhruva Gole wrote:

> Fixes: 1b74dd64c861 ("spi: Add Socionext F_OSPI SPI flash controller driver")

This is clearly not a good fit for using Fixes.

> Allignment issues in all the macro definitions of this driver have been
> fixed for better asthetics

In what way?

> -#define OSPI_PROT_CTL_INDIR			0x00
> -#define   OSPI_PROT_MODE_DATA_MASK		GENMASK(31, 30)
> -#define   OSPI_PROT_MODE_ALT_MASK		GENMASK(29, 28)
> -#define   OSPI_PROT_MODE_ADDR_MASK		GENMASK(27, 26)
> -#define   OSPI_PROT_MODE_CODE_MASK		GENMASK(25, 24)
> -#define     OSPI_PROT_MODE_SINGLE		0
> -#define     OSPI_PROT_MODE_DUAL			1
> -#define     OSPI_PROT_MODE_QUAD			2
> -#define     OSPI_PROT_MODE_OCTAL		3

> +#define	OSPI_PROT_CTL_INDIR			0x00
> +#define	OSPI_PROT_MODE_DATA_MASK		GENMASK(31, 30)
> +#define	OSPI_PROT_MODE_ALT_MASK			GENMASK(29, 28)
> +#define	OSPI_PROT_MODE_ADDR_MASK		GENMASK(27, 26)
> +#define	OSPI_PROT_MODE_CODE_MASK		GENMASK(25, 24)
> +#define	OSPI_PROT_MODE_SINGLE			0
> +#define	OSPI_PROT_MODE_DUAL			1
> +#define	OSPI_PROT_MODE_QUAD			2
> +#define	OSPI_PROT_MODE_OCTAL			3

As far as I can tell this is just removing all the intentation which
differentiates register, field and value - that looks like a clear step
back?
Mark Brown March 1, 2023, 6:21 p.m. UTC | #2 
On Wed, Mar 01, 2023 at 10:49:31AM +0530, dhruva gole wrote:
> On 27/02/23 19:39, Mark Brown wrote:
> > On Thu, Feb 23, 2023 at 03:59:18PM +0530, Dhruva Gole wrote:

> > > Allignment issues in all the macro definitions of this driver have been
> > > fixed for better asthetics

> > In what way?

> In my humble opinion, the spacing between the MACRO names

> and their values seemed a bit OFF. Like there lacked

> consistency for example:

> OSPI_PROT_MODE_QUAD			2
> OSPI_PROT_MODE_OCTAL		3

> Here we can see 3 is at a shorter length compared to 2 from their respective macros.

These look perfectly lined up for me.  I suspect you may have your tab
size set to something other than 8.
diff mbox series

Patch

diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c
index 348c6e1edd38..6bd0d4945aa0 100644
--- a/drivers/spi/spi-sn-f-ospi.c
+++ b/drivers/spi/spi-sn-f-ospi.c
@@ -16,96 +16,96 @@ 
 #include <linux/spi/spi-mem.h>
 
 /* Registers */
-#define OSPI_PROT_CTL_INDIR			0x00
-#define   OSPI_PROT_MODE_DATA_MASK		GENMASK(31, 30)
-#define   OSPI_PROT_MODE_ALT_MASK		GENMASK(29, 28)
-#define   OSPI_PROT_MODE_ADDR_MASK		GENMASK(27, 26)
-#define   OSPI_PROT_MODE_CODE_MASK		GENMASK(25, 24)
-#define     OSPI_PROT_MODE_SINGLE		0
-#define     OSPI_PROT_MODE_DUAL			1
-#define     OSPI_PROT_MODE_QUAD			2
-#define     OSPI_PROT_MODE_OCTAL		3
-#define   OSPI_PROT_DATA_RATE_DATA		BIT(23)
-#define   OSPI_PROT_DATA_RATE_ALT		BIT(22)
-#define   OSPI_PROT_DATA_RATE_ADDR		BIT(21)
-#define   OSPI_PROT_DATA_RATE_CODE		BIT(20)
-#define     OSPI_PROT_SDR			0
-#define     OSPI_PROT_DDR			1
-#define   OSPI_PROT_BIT_POS_DATA		BIT(19)
-#define   OSPI_PROT_BIT_POS_ALT			BIT(18)
-#define   OSPI_PROT_BIT_POS_ADDR		BIT(17)
-#define   OSPI_PROT_BIT_POS_CODE		BIT(16)
-#define   OSPI_PROT_SAMP_EDGE			BIT(12)
-#define   OSPI_PROT_DATA_UNIT_MASK		GENMASK(11, 10)
-#define     OSPI_PROT_DATA_UNIT_1B		0
-#define     OSPI_PROT_DATA_UNIT_2B		1
-#define     OSPI_PROT_DATA_UNIT_4B		3
-#define   OSPI_PROT_TRANS_DIR_WRITE		BIT(9)
-#define   OSPI_PROT_DATA_EN			BIT(8)
-#define   OSPI_PROT_ALT_SIZE_MASK		GENMASK(7, 5)
-#define   OSPI_PROT_ADDR_SIZE_MASK		GENMASK(4, 2)
-#define   OSPI_PROT_CODE_SIZE_MASK		GENMASK(1, 0)
-
-#define OSPI_CLK_CTL				0x10
-#define   OSPI_CLK_CTL_BOOT_INT_CLK_EN		BIT(16)
-#define   OSPI_CLK_CTL_PHA			BIT(12)
-#define     OSPI_CLK_CTL_PHA_180		0
-#define     OSPI_CLK_CTL_PHA_90			1
-#define   OSPI_CLK_CTL_DIV			GENMASK(9, 8)
-#define     OSPI_CLK_CTL_DIV_1			0
-#define     OSPI_CLK_CTL_DIV_2			1
-#define     OSPI_CLK_CTL_DIV_4			2
-#define     OSPI_CLK_CTL_DIV_8			3
-#define   OSPI_CLK_CTL_INT_CLK_EN		BIT(0)
-
-#define OSPI_CS_CTL1				0x14
-#define OSPI_CS_CTL2				0x18
-#define OSPI_SSEL				0x20
-#define OSPI_CMD_IDX_INDIR			0x40
-#define OSPI_ADDR				0x50
-#define OSPI_ALT_INDIR				0x60
-#define OSPI_DMY_INDIR				0x70
-#define OSPI_DAT				0x80
-#define OSPI_DAT_SWP_INDIR			0x90
-
-#define OSPI_DAT_SIZE_INDIR			0xA0
-#define   OSPI_DAT_SIZE_EN			BIT(15)
-#define   OSPI_DAT_SIZE_MASK			GENMASK(10, 0)
-#define   OSPI_DAT_SIZE_MAX			(OSPI_DAT_SIZE_MASK + 1)
-
-#define OSPI_TRANS_CTL				0xC0
-#define   OSPI_TRANS_CTL_STOP_REQ		BIT(1)	/* RW1AC */
-#define   OSPI_TRANS_CTL_START_REQ		BIT(0)	/* RW1AC */
-
-#define OSPI_ACC_MODE				0xC4
-#define   OSPI_ACC_MODE_BOOT_DISABLE		BIT(0)
-
-#define OSPI_SWRST				0xD0
-#define   OSPI_SWRST_INDIR_WRITE_FIFO		BIT(9)	/* RW1AC */
-#define   OSPI_SWRST_INDIR_READ_FIFO		BIT(8)	/* RW1AC */
-
-#define OSPI_STAT				0xE0
-#define   OSPI_STAT_IS_AXI_WRITING		BIT(10)
-#define   OSPI_STAT_IS_AXI_READING		BIT(9)
-#define   OSPI_STAT_IS_SPI_INT_CLK_STOP		BIT(4)
-#define   OSPI_STAT_IS_SPI_IDLE			BIT(3)
-
-#define OSPI_IRQ				0xF0
-#define   OSPI_IRQ_CS_DEASSERT			BIT(8)
-#define   OSPI_IRQ_WRITE_BUF_READY		BIT(2)
-#define   OSPI_IRQ_READ_BUF_READY		BIT(1)
-#define   OSPI_IRQ_CS_TRANS_COMP		BIT(0)
-#define   OSPI_IRQ_ALL				\
+#define	OSPI_PROT_CTL_INDIR			0x00
+#define	OSPI_PROT_MODE_DATA_MASK		GENMASK(31, 30)
+#define	OSPI_PROT_MODE_ALT_MASK			GENMASK(29, 28)
+#define	OSPI_PROT_MODE_ADDR_MASK		GENMASK(27, 26)
+#define	OSPI_PROT_MODE_CODE_MASK		GENMASK(25, 24)
+#define	OSPI_PROT_MODE_SINGLE			0
+#define	OSPI_PROT_MODE_DUAL			1
+#define	OSPI_PROT_MODE_QUAD			2
+#define	OSPI_PROT_MODE_OCTAL			3
+#define	OSPI_PROT_DATA_RATE_DATA		BIT(23)
+#define	OSPI_PROT_DATA_RATE_ALT			BIT(22)
+#define	OSPI_PROT_DATA_RATE_ADDR		BIT(21)
+#define	OSPI_PROT_DATA_RATE_CODE		BIT(20)
+#define	OSPI_PROT_SDR				0
+#define	OSPI_PROT_DDR				1
+#define	OSPI_PROT_BIT_POS_DATA			BIT(19)
+#define	OSPI_PROT_BIT_POS_ALT			BIT(18)
+#define	OSPI_PROT_BIT_POS_ADDR			BIT(17)
+#define	OSPI_PROT_BIT_POS_CODE			BIT(16)
+#define	OSPI_PROT_SAMP_EDGE			BIT(12)
+#define	OSPI_PROT_DATA_UNIT_MASK		GENMASK(11, 10)
+#define	OSPI_PROT_DATA_UNIT_1B			0
+#define	OSPI_PROT_DATA_UNIT_2B			1
+#define	OSPI_PROT_DATA_UNIT_4B			3
+#define	OSPI_PROT_TRANS_DIR_WRITE		BIT(9)
+#define	OSPI_PROT_DATA_EN			BIT(8)
+#define	OSPI_PROT_ALT_SIZE_MASK			GENMASK(7, 5)
+#define	OSPI_PROT_ADDR_SIZE_MASK		GENMASK(4, 2)
+#define	OSPI_PROT_CODE_SIZE_MASK		GENMASK(1, 0)
+
+#define	OSPI_CLK_CTL				0x10
+#define	OSPI_CLK_CTL_BOOT_INT_CLK_EN		BIT(16)
+#define	OSPI_CLK_CTL_PHA			BIT(12)
+#define	OSPI_CLK_CTL_PHA_180			0
+#define	OSPI_CLK_CTL_PHA_90			1
+#define	OSPI_CLK_CTL_DIV			GENMASK(9, 8)
+#define	OSPI_CLK_CTL_DIV_1			0
+#define	OSPI_CLK_CTL_DIV_2			1
+#define	OSPI_CLK_CTL_DIV_4			2
+#define	OSPI_CLK_CTL_DIV_8			3
+#define	OSPI_CLK_CTL_INT_CLK_EN			BIT(0)
+
+#define	OSPI_CS_CTL1				0x14
+#define	OSPI_CS_CTL2				0x18
+#define	OSPI_SSEL				0x20
+#define	OSPI_CMD_IDX_INDIR			0x40
+#define	OSPI_ADDR				0x50
+#define	OSPI_ALT_INDIR				0x60
+#define	OSPI_DMY_INDIR				0x70
+#define	OSPI_DAT				0x80
+#define	OSPI_DAT_SWP_INDIR			0x90
+
+#define	OSPI_DAT_SIZE_INDIR			0xA0
+#define	OSPI_DAT_SIZE_EN			BIT(15)
+#define	OSPI_DAT_SIZE_MASK			GENMASK(10, 0)
+#define	OSPI_DAT_SIZE_MAX			(OSPI_DAT_SIZE_MASK + 1)
+
+#define	OSPI_TRANS_CTL				0xC0
+#define	OSPI_TRANS_CTL_STOP_REQ			BIT(1)	/* RW1AC */
+#define	OSPI_TRANS_CTL_START_REQ		BIT(0)	/* RW1AC */
+
+#define	OSPI_ACC_MODE				0xC4
+#define	OSPI_ACC_MODE_BOOT_DISABLE		BIT(0)
+
+#define	OSPI_SWRST				0xD0
+#define	OSPI_SWRST_INDIR_WRITE_FIFO		BIT(9)	/* RW1AC */
+#define	OSPI_SWRST_INDIR_READ_FIFO		BIT(8)	/* RW1AC */
+
+#define	OSPI_STAT				0xE0
+#define	OSPI_STAT_IS_AXI_WRITING		BIT(10)
+#define	OSPI_STAT_IS_AXI_READING		BIT(9)
+#define	OSPI_STAT_IS_SPI_INT_CLK_STOP		BIT(4)
+#define	OSPI_STAT_IS_SPI_IDLE			BIT(3)
+
+#define	OSPI_IRQ				0xF0
+#define	OSPI_IRQ_CS_DEASSERT			BIT(8)
+#define	OSPI_IRQ_WRITE_BUF_READY		BIT(2)
+#define	OSPI_IRQ_READ_BUF_READY			BIT(1)
+#define	OSPI_IRQ_CS_TRANS_COMP			BIT(0)
+#define	OSPI_IRQ_ALL				\
 		(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \
 		 | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP)
 
-#define OSPI_IRQ_STAT_EN			0xF4
-#define OSPI_IRQ_SIG_EN				0xF8
+#define	OSPI_IRQ_STAT_EN			0xF4
+#define	OSPI_IRQ_SIG_EN				0xF8
 
 /* Parameters */
-#define OSPI_NUM_CS				4
-#define OSPI_DUMMY_CYCLE_MAX			255
-#define OSPI_WAIT_MAX_MSEC			100
+#define	OSPI_NUM_CS				4
+#define	OSPI_DUMMY_CYCLE_MAX			255
+#define	OSPI_WAIT_MAX_MSEC			100
 
 struct f_ospi {
 	void __iomem *base;