diff mbox series

[v3,7/8] KVM: selftests: Add XFEATURE masks to common code

Message ID 20230224223607.1580880-8-aaronlewis@google.com (mailing list archive)
State New, archived
Headers show
Series Clean up the supported xfeatures | expand

Commit Message

Aaron Lewis Feb. 24, 2023, 10:36 p.m. UTC 
Add XFEATURE masks to processor.h to make them more broadly available
in KVM selftests.

Use the names from the kernel's fpu/types.h for consistency, i.e.
rename XTILECFG and XTILEDATA to XTILE_CFG and XTILE_DATA respectively.

Signed-off-by: Aaron Lewis <aaronlewis@google.com>
---
 .../selftests/kvm/include/x86_64/processor.h  | 17 ++++++++++++++
 tools/testing/selftests/kvm/x86_64/amx_test.c | 22 +++++++------------
 2 files changed, 25 insertions(+), 14 deletions(-)

Comments

Mingwei Zhang March 3, 2023, 9:16 p.m. UTC | #1 
On Fri, Feb 24, 2023, Aaron Lewis wrote:
> Add XFEATURE masks to processor.h to make them more broadly available
> in KVM selftests.
> 
> Use the names from the kernel's fpu/types.h for consistency, i.e.
> rename XTILECFG and XTILEDATA to XTILE_CFG and XTILE_DATA respectively.
> 
> Signed-off-by: Aaron Lewis <aaronlewis@google.com>
> ---
>  .../selftests/kvm/include/x86_64/processor.h  | 17 ++++++++++++++
>  tools/testing/selftests/kvm/x86_64/amx_test.c | 22 +++++++------------
>  2 files changed, 25 insertions(+), 14 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
> index 62dc54c8e0c4..ebe83cfe521c 100644
> --- a/tools/testing/selftests/kvm/include/x86_64/processor.h
> +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
> @@ -48,6 +48,23 @@ extern bool host_cpu_is_amd;
>  #define X86_CR4_SMAP		(1ul << 21)
>  #define X86_CR4_PKE		(1ul << 22)
>  
> +#define XFEATURE_MASK_FP		BIT_ULL(0)
> +#define XFEATURE_MASK_SSE		BIT_ULL(1)
> +#define XFEATURE_MASK_YMM		BIT_ULL(2)
> +#define XFEATURE_MASK_BNDREGS		BIT_ULL(3)
> +#define XFEATURE_MASK_BNDCSR		BIT_ULL(4)
> +#define XFEATURE_MASK_OPMASK		BIT_ULL(5)
> +#define XFEATURE_MASK_ZMM_Hi256		BIT_ULL(6)
> +#define XFEATURE_MASK_Hi16_ZMM		BIT_ULL(7)
> +#define XFEATURE_MASK_XTILE_CFG		BIT_ULL(17)
> +#define XFEATURE_MASK_XTILE_DATA	BIT_ULL(18)
> +
> +#define XFEATURE_MASK_AVX512		(XFEATURE_MASK_OPMASK | \
> +					 XFEATURE_MASK_ZMM_Hi256 | \
> +					 XFEATURE_MASK_Hi16_ZMM)
> +#define XFEATURE_MASK_XTILE		(XFEATURE_MASK_XTILE_DATA | \
> +					 XFEATURE_MASK_XTILE_CFG)
> +
>  /* Note, these are ordered alphabetically to match kvm_cpuid_entry2.  Eww. */
>  enum cpuid_output_regs {
>  	KVM_CPUID_EAX,
> diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c
> index 4b733ad21831..14a7656620d5 100644
> --- a/tools/testing/selftests/kvm/x86_64/amx_test.c
> +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c
> @@ -33,12 +33,6 @@
>  #define MAX_TILES			16
>  #define RESERVED_BYTES			14
>  
> -#define XFEATURE_XTILECFG		17
> -#define XFEATURE_XTILEDATA		18
> -#define XFEATURE_MASK_XTILECFG		(1 << XFEATURE_XTILECFG)
> -#define XFEATURE_MASK_XTILEDATA		(1 << XFEATURE_XTILEDATA)
> -#define XFEATURE_MASK_XTILE		(XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
> -
>  #define XSAVE_HDR_OFFSET		512
>  
>  struct xsave_data {
> @@ -187,14 +181,14 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
>  	__tilerelease();
>  	GUEST_SYNC(5);
>  	/* bit 18 not in the XCOMP_BV after xsavec() */
> -	set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA);
> -	__xsavec(xsave_data, XFEATURE_MASK_XTILEDATA);
> -	GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0);
> +	set_xstatebv(xsave_data, XFEATURE_MASK_XTILE_DATA);
> +	__xsavec(xsave_data, XFEATURE_MASK_XTILE_DATA);
> +	GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILE_DATA) == 0);
>  
>  	/* xfd=0x40000, disable amx tiledata */
> -	wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
> +	wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA);
>  	GUEST_SYNC(6);
> -	GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
> +	GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA);
>  	set_tilecfg(amx_cfg);
>  	__ldtilecfg(amx_cfg);
>  	/* Trigger #NM exception */
> @@ -206,11 +200,11 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
>  
>  void guest_nm_handler(struct ex_regs *regs)
>  {
> -	/* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */
> +	/* Check if #NM is triggered by XFEATURE_MASK_XTILE_DATA */
>  	GUEST_SYNC(7);
> -	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
> +	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
>  	GUEST_SYNC(8);
> -	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
> +	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
>  	/* Clear xfd_err */
>  	wrmsr(MSR_IA32_XFD_ERR, 0);
>  	/* xfd=0, enable amx */
> -- 
> 2.39.2.637.g21b0678d19-goog
> 
Can I take your commit into my series? This seems to be closely related
with amx_test itself without much relationship with the xcr0 test.
Thoughts?
Aaron Lewis March 3, 2023, 10:25 p.m. UTC | #2 
On Fri, Mar 3, 2023 at 9:16 PM Mingwei Zhang <mizhang@google.com> wrote:
>
> On Fri, Feb 24, 2023, Aaron Lewis wrote:
> > Add XFEATURE masks to processor.h to make them more broadly available
> > in KVM selftests.
> >
> > Use the names from the kernel's fpu/types.h for consistency, i.e.
> > rename XTILECFG and XTILEDATA to XTILE_CFG and XTILE_DATA respectively.
> >
> > Signed-off-by: Aaron Lewis <aaronlewis@google.com>
> > ---
> >  .../selftests/kvm/include/x86_64/processor.h  | 17 ++++++++++++++
> >  tools/testing/selftests/kvm/x86_64/amx_test.c | 22 +++++++------------
> >  2 files changed, 25 insertions(+), 14 deletions(-)
> >
> > diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
> > index 62dc54c8e0c4..ebe83cfe521c 100644
> > --- a/tools/testing/selftests/kvm/include/x86_64/processor.h
> > +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
> > @@ -48,6 +48,23 @@ extern bool host_cpu_is_amd;
> >  #define X86_CR4_SMAP         (1ul << 21)
> >  #define X86_CR4_PKE          (1ul << 22)
> >
> > +#define XFEATURE_MASK_FP             BIT_ULL(0)
> > +#define XFEATURE_MASK_SSE            BIT_ULL(1)
> > +#define XFEATURE_MASK_YMM            BIT_ULL(2)
> > +#define XFEATURE_MASK_BNDREGS                BIT_ULL(3)
> > +#define XFEATURE_MASK_BNDCSR         BIT_ULL(4)
> > +#define XFEATURE_MASK_OPMASK         BIT_ULL(5)
> > +#define XFEATURE_MASK_ZMM_Hi256              BIT_ULL(6)
> > +#define XFEATURE_MASK_Hi16_ZMM               BIT_ULL(7)
> > +#define XFEATURE_MASK_XTILE_CFG              BIT_ULL(17)
> > +#define XFEATURE_MASK_XTILE_DATA     BIT_ULL(18)
> > +
> > +#define XFEATURE_MASK_AVX512         (XFEATURE_MASK_OPMASK | \
> > +                                      XFEATURE_MASK_ZMM_Hi256 | \
> > +                                      XFEATURE_MASK_Hi16_ZMM)
> > +#define XFEATURE_MASK_XTILE          (XFEATURE_MASK_XTILE_DATA | \
> > +                                      XFEATURE_MASK_XTILE_CFG)
> > +
> >  /* Note, these are ordered alphabetically to match kvm_cpuid_entry2.  Eww. */
> >  enum cpuid_output_regs {
> >       KVM_CPUID_EAX,
> > diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c
> > index 4b733ad21831..14a7656620d5 100644
> > --- a/tools/testing/selftests/kvm/x86_64/amx_test.c
> > +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c
> > @@ -33,12 +33,6 @@
> >  #define MAX_TILES                    16
> >  #define RESERVED_BYTES                       14
> >
> > -#define XFEATURE_XTILECFG            17
> > -#define XFEATURE_XTILEDATA           18
> > -#define XFEATURE_MASK_XTILECFG               (1 << XFEATURE_XTILECFG)
> > -#define XFEATURE_MASK_XTILEDATA              (1 << XFEATURE_XTILEDATA)
> > -#define XFEATURE_MASK_XTILE          (XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
> > -
> >  #define XSAVE_HDR_OFFSET             512
> >
> >  struct xsave_data {
> > @@ -187,14 +181,14 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
> >       __tilerelease();
> >       GUEST_SYNC(5);
> >       /* bit 18 not in the XCOMP_BV after xsavec() */
> > -     set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA);
> > -     __xsavec(xsave_data, XFEATURE_MASK_XTILEDATA);
> > -     GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0);
> > +     set_xstatebv(xsave_data, XFEATURE_MASK_XTILE_DATA);
> > +     __xsavec(xsave_data, XFEATURE_MASK_XTILE_DATA);
> > +     GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILE_DATA) == 0);
> >
> >       /* xfd=0x40000, disable amx tiledata */
> > -     wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
> > +     wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA);
> >       GUEST_SYNC(6);
> > -     GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
> > +     GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA);
> >       set_tilecfg(amx_cfg);
> >       __ldtilecfg(amx_cfg);
> >       /* Trigger #NM exception */
> > @@ -206,11 +200,11 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
> >
> >  void guest_nm_handler(struct ex_regs *regs)
> >  {
> > -     /* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */
> > +     /* Check if #NM is triggered by XFEATURE_MASK_XTILE_DATA */
> >       GUEST_SYNC(7);
> > -     GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
> > +     GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
> >       GUEST_SYNC(8);
> > -     GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
> > +     GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
> >       /* Clear xfd_err */
> >       wrmsr(MSR_IA32_XFD_ERR, 0);
> >       /* xfd=0, enable amx */
> > --
> > 2.39.2.637.g21b0678d19-goog
> >
> Can I take your commit into my series? This seems to be closely related
> with amx_test itself without much relationship with the xcr0 test.
> Thoughts?

Yes, please do.  I still need to have it here to have access to the
common xfeatures.
Mingwei Zhang March 7, 2023, 4:33 p.m. UTC | #3 
> > Can I take your commit into my series? This seems to be closely related
> > with amx_test itself without much relationship with the xcr0 test.
> > Thoughts?
>
> Yes, please do.  I still need to have it here to have access to the
> common xfeatures.

hmm, you are right. Then, this series should go before the selftest series.

Thanks.
-Mingwei
diff mbox series

Patch

diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
index 62dc54c8e0c4..ebe83cfe521c 100644
--- a/tools/testing/selftests/kvm/include/x86_64/processor.h
+++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
@@ -48,6 +48,23 @@  extern bool host_cpu_is_amd;
 #define X86_CR4_SMAP		(1ul << 21)
 #define X86_CR4_PKE		(1ul << 22)
 
+#define XFEATURE_MASK_FP		BIT_ULL(0)
+#define XFEATURE_MASK_SSE		BIT_ULL(1)
+#define XFEATURE_MASK_YMM		BIT_ULL(2)
+#define XFEATURE_MASK_BNDREGS		BIT_ULL(3)
+#define XFEATURE_MASK_BNDCSR		BIT_ULL(4)
+#define XFEATURE_MASK_OPMASK		BIT_ULL(5)
+#define XFEATURE_MASK_ZMM_Hi256		BIT_ULL(6)
+#define XFEATURE_MASK_Hi16_ZMM		BIT_ULL(7)
+#define XFEATURE_MASK_XTILE_CFG		BIT_ULL(17)
+#define XFEATURE_MASK_XTILE_DATA	BIT_ULL(18)
+
+#define XFEATURE_MASK_AVX512		(XFEATURE_MASK_OPMASK | \
+					 XFEATURE_MASK_ZMM_Hi256 | \
+					 XFEATURE_MASK_Hi16_ZMM)
+#define XFEATURE_MASK_XTILE		(XFEATURE_MASK_XTILE_DATA | \
+					 XFEATURE_MASK_XTILE_CFG)
+
 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2.  Eww. */
 enum cpuid_output_regs {
 	KVM_CPUID_EAX,
diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c
index 4b733ad21831..14a7656620d5 100644
--- a/tools/testing/selftests/kvm/x86_64/amx_test.c
+++ b/tools/testing/selftests/kvm/x86_64/amx_test.c
@@ -33,12 +33,6 @@ 
 #define MAX_TILES			16
 #define RESERVED_BYTES			14
 
-#define XFEATURE_XTILECFG		17
-#define XFEATURE_XTILEDATA		18
-#define XFEATURE_MASK_XTILECFG		(1 << XFEATURE_XTILECFG)
-#define XFEATURE_MASK_XTILEDATA		(1 << XFEATURE_XTILEDATA)
-#define XFEATURE_MASK_XTILE		(XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
-
 #define XSAVE_HDR_OFFSET		512
 
 struct xsave_data {
@@ -187,14 +181,14 @@  static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
 	__tilerelease();
 	GUEST_SYNC(5);
 	/* bit 18 not in the XCOMP_BV after xsavec() */
-	set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA);
-	__xsavec(xsave_data, XFEATURE_MASK_XTILEDATA);
-	GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0);
+	set_xstatebv(xsave_data, XFEATURE_MASK_XTILE_DATA);
+	__xsavec(xsave_data, XFEATURE_MASK_XTILE_DATA);
+	GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILE_DATA) == 0);
 
 	/* xfd=0x40000, disable amx tiledata */
-	wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
+	wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA);
 	GUEST_SYNC(6);
-	GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
+	GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA);
 	set_tilecfg(amx_cfg);
 	__ldtilecfg(amx_cfg);
 	/* Trigger #NM exception */
@@ -206,11 +200,11 @@  static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
 
 void guest_nm_handler(struct ex_regs *regs)
 {
-	/* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */
+	/* Check if #NM is triggered by XFEATURE_MASK_XTILE_DATA */
 	GUEST_SYNC(7);
-	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
+	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
 	GUEST_SYNC(8);
-	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
+	GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA);
 	/* Clear xfd_err */
 	wrmsr(MSR_IA32_XFD_ERR, 0);
 	/* xfd=0, enable amx */