| Message ID | 20230302133709.30373-7-Jonathan.Cameron@huawei.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/cxl: RAS error emulation and injection | expand |
On Thu, Mar 02, 2023 at 01:37:07PM +0000, Jonathan Cameron wrote: > As these are about to be modified, fix the endian handle for > this set of registers rather than making it worse. > > Note that CXL is currently only supported in QEMU on > x86 (arm64 patches out of tree) so we aren't going to yet hit > an problems with big endian. However it is good to avoid making > things worse for that support in the future. > > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- Reviewed-by: Fan Ni <fan.ni@samsung.com> > hw/cxl/cxl-component-utils.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 3edd303a33..737b4764b9 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) > * Error status is RW1C but given bits are not yet set, it can > * be handled as RO. > */ > - reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; > + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); > /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ > - reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; > - write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; > - reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; > - write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; > - reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; > - reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; > - write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; > + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); > + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); > + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); > + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); > + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); > + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); > + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); > /* CXL switches and devices must set */ > - reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; > + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); > } > > static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > -- > 2.37.2 > >
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 3edd303a33..737b4764b9 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) * Error status is RW1C but given bits are not yet set, it can * be handled as RO. */ - reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ - reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; - reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; - write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); /* CXL switches and devices must set */ - reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); } static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,