| Message ID | 20230306220259.7748-1-palmer@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 6 Mar 2023 at 22:04, Palmer Dabbelt <palmer@rivosinc.com> wrote: > > The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0: > > configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46 +0000) > > are available in the Git repository at: > > https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306 > > for you to fetch changes up to 47fc340010335bc2549bc1f07e5fd85d86a2b9f9: > > MAINTAINERS: Add entry for RISC-V ACPI (2023-03-06 11:35:08 -0800) > > ---------------------------------------------------------------- > Sixth RISC-V PR for 8.0 > > * Support for the Zicbiom, ZCicboz, and Zicbop extensions. > * OpenSBI has been updated to version 1.2, see > <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for > the release notes. > * Support for setting the virtual address width (ie, sv39/sv48/sv57) on > the command line. > * Support for ACPI on RISC-V. > > ---------------------------------------------------------------- > Sorry for the flurry of late pull requests, but we had a few stragglers > (ACPI due to reviews and OpenSBI due to the CI failures, the others I'd > largely just missed). I don't intend on sending anything else for the > soft freeze, this is already well past late enough for me ;) > > I'm not exactly sure what happened, but this tag managed to pass CI > <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797833683> despite > me not really doing anything to fix the timeouts -- hopefully that was > just a result of me having gotten unlucky or missing a larger timeout in > my fork, but sorry if I've managed to screw something up. > > I have no merge conflicts and the tests are passing locally. I've got a > CI run here > <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797922220>, but I > figured I'd just send this now given that I had one pass from just the > tag. > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0: configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46 +0000) are available in the Git repository at: https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306 for you to fetch changes up to 47fc340010335bc2549bc1f07e5fd85d86a2b9f9: MAINTAINERS: Add entry for RISC-V ACPI (2023-03-06 11:35:08 -0800) ---------------------------------------------------------------- Sixth RISC-V PR for 8.0 * Support for the Zicbiom, ZCicboz, and Zicbop extensions. * OpenSBI has been updated to version 1.2, see <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for the release notes. * Support for setting the virtual address width (ie, sv39/sv48/sv57) on the command line. * Support for ACPI on RISC-V. ---------------------------------------------------------------- Sorry for the flurry of late pull requests, but we had a few stragglers (ACPI due to reviews and OpenSBI due to the CI failures, the others I'd largely just missed). I don't intend on sending anything else for the soft freeze, this is already well past late enough for me ;) I'm not exactly sure what happened, but this tag managed to pass CI <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797833683> despite me not really doing anything to fix the timeouts -- hopefully that was just a result of me having gotten unlucky or missing a larger timeout in my fork, but sorry if I've managed to screw something up. I have no merge conflicts and the tests are passing locally. I've got a CI run here <https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797922220>, but I figured I'd just send this now given that I had one pass from just the tag. ---------------------------------------------------------------- Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Introduce satp mode hw capabilities riscv: Correctly set the device-tree entry 'mmu-type' Anup Patel (1): hw/riscv/virt.c: add cbo[mz]-block-size fdt properties Bin Meng (1): roms/opensbi: Upgrade from v1.1 to v1.2 Christoph Muellner (3): target/riscv: implement Zicboz extension target/riscv: implement Zicbom extension target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder Ivan Klokov (1): disas/riscv Fix ctzw disassemble Mayuresh Chitale (2): target/riscv: cpu: Implement get_arch_id callback hw: intc: Use cpu_by_arch_id to fetch CPU state Palmer Dabbelt (1): gitlab/opensbi: Move to docker:stable Sunil V L (8): hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields hw/riscv/virt: Add a switch to disable ACPI hw/riscv/virt: Add memmap pointer to RiscVVirtState hw/riscv/virt: Enable basic ACPI infrastructure hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT hw/riscv/virt: virt-acpi-build.c: Add RHCT Table hw/riscv/virt.c: Initialize the ACPI tables MAINTAINERS: Add entry for RISC-V ACPI .gitlab-ci.d/opensbi.yml | 4 +- .gitlab-ci.d/opensbi/Dockerfile | 1 + MAINTAINERS | 18 +- disas/riscv.c | 2 +- hw/intc/riscv_aclint.c | 16 +- hw/intc/riscv_aplic.c | 4 +- hw/intc/riscv_imsic.c | 6 +- hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 + hw/riscv/virt-acpi-build.c | 416 +++++++++++++++++++++++++ hw/riscv/virt.c | 70 ++++- include/hw/riscv/virt.h | 6 + pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 117704 -> 123072 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 115344 -> 121800 bytes roms/opensbi | 2 +- target/riscv/cpu.c | 303 +++++++++++++++++- target/riscv/cpu.h | 29 ++ target/riscv/csr.c | 29 +- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 16 +- target/riscv/insn_trans/trans_rvzicbo.c.inc | 57 ++++ target/riscv/op_helper.c | 135 ++++++++ target/riscv/translate.c | 1 + 23 files changed, 1061 insertions(+), 61 deletions(-) create mode 100644 hw/riscv/virt-acpi-build.c create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc