diff mbox series

[7/8] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw

Message ID 20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org (mailing list archive)
State New, archived
Delegated to: viresh kumar
Headers show
Series qcom-cpufreq-hw binding improvements | expand

Commit Message

Konrad Dybcio March 8, 2023, 1:27 a.m. UTC
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Luca Weiss March 8, 2023, 10:35 a.m. UTC | #1
Hi Konrad,

On Wed Mar 8, 2023 at 2:27 AM CET, Konrad Dybcio wrote:
> Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 1e1d366c92c1..c18ca947618e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1995,7 +1995,7 @@ osm_l3: interconnect@18321000 {
>  		};
>  
>  		cpufreq_hw: cpufreq@18323000 {
> -			compatible = "qcom,cpufreq-hw";
> +			compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
>  			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
>  			reg-names = "freq-domain0", "freq-domain1";
>  			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>
> -- 
> 2.39.2
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 1e1d366c92c1..c18ca947618e 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1995,7 +1995,7 @@  osm_l3: interconnect@18321000 {
 		};
 
 		cpufreq_hw: cpufreq@18323000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
 			reg-names = "freq-domain0", "freq-domain1";
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;