| Message ID | 20230306191535.1917656-4-sean.anderson@seco.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | phy: Add support for Lynx 10G SerDes | expand |
Hi, On Mon, 6 Mar 2023 at 20:16, Sean Anderson <sean.anderson@seco.com> wrote: > > This is a generic binding for simple MMIO GPIO controllers. Although we > have a single driver for these controllers, they were previously spread > over several files. Consolidate them. The register descriptions are > adapted from the comments in the source. There is no set order for the > registers, so I have not specified one. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v10: > - New > > .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- > .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ > .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- > .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- > 4 files changed, 137 insertions(+), 91 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > index 4d69f79df859..e11f4af49c52 100644 > --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml You are (re-)moving the compatible this file is named after, you might want to rename the file as well then. Going by age bcm6358 would be the next oldest one (bcm6318 would be the newest, despite the lowest number). Regards Jonas
On 3/6/23 15:51, Jonas Gorski wrote: > Hi, > > On Mon, 6 Mar 2023 at 20:16, Sean Anderson <sean.anderson@seco.com> wrote: >> >> This is a generic binding for simple MMIO GPIO controllers. Although we >> have a single driver for these controllers, they were previously spread >> over several files. Consolidate them. The register descriptions are >> adapted from the comments in the source. There is no set order for the >> registers, so I have not specified one. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v10: >> - New >> >> .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- >> .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ >> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- >> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- >> 4 files changed, 137 insertions(+), 91 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >> delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt >> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt >> >> diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml >> index 4d69f79df859..e11f4af49c52 100644 >> --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml >> +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > > You are (re-)moving the compatible this file is named after, you might > want to rename the file as well then. Going by age bcm6358 would be > the next oldest one (bcm6318 would be the newest, despite the lowest > number). I can do that. Would it be fine to rename to e.g. brcm,bcm63xx-gpio.yaml? --Sean
Hi Sean, thanks for doing this. I never got around to because time. On Mon, Mar 6, 2023 at 8:16 PM Sean Anderson <sean.anderson@seco.com> wrote: > This is a generic binding for simple MMIO GPIO controllers. Although we > have a single driver for these controllers, they were previously spread > over several files. Consolidate them. The register descriptions are > adapted from the comments in the source. There is no set order for the > registers, so I have not specified one. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> (...) > + compatible: > + enum: > + - brcm,bcm6345-gpio # Broadcom BCM6345 GPIO controller > + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller > + - ni,169445-nand-gpio # National Instruments 169445 GPIO NAND controller I think you can inline description: statements in the enum instead of the # hash comments, however IIRC you have to use oneOf and const: to do it, like I do in Documentation/devicetree/bindings/input/touchscreen/cypress,cy8ctma340.yaml but don't overinvest in this if it is cumbersome. Either way: Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On 06/03/2023 20:15, Sean Anderson wrote: > This is a generic binding for simple MMIO GPIO controllers. Although we > have a single driver for these controllers, they were previously spread > over several files. Consolidate them. The register descriptions are > adapted from the comments in the source. There is no set order for the > registers, so I have not specified one. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v10: > - New > > .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- > .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ > .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- > .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- > 4 files changed, 137 insertions(+), 91 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/ https://lore.kernel.org/all/9bc9349d6e13d81c6200b0cd8fa20c76263043f6.1462543458.git.chunkeey@googlemail.com/ Best regards, Krzysztof
Hi Krzysztof, On 3/7/23 03:42, Krzysztof Kozlowski wrote: > On 06/03/2023 20:15, Sean Anderson wrote: >> This is a generic binding for simple MMIO GPIO controllers. Although we >> have a single driver for these controllers, they were previously spread >> over several files. Consolidate them. The register descriptions are >> adapted from the comments in the source. There is no set order for the >> registers, so I have not specified one. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v10: >> - New >> >> .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- >> .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ >> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- >> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- >> 4 files changed, 137 insertions(+), 91 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >> delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt >> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > > https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/ Thanks for linking to that. I believe this patch should be applied instead of that one because - It documents all the registers, which were previously only documented in the driver - It handles the endianness properties. - It consolidates the various descriptions of this binding into one schema. --Sean
On 07/03/2023 16:35, Sean Anderson wrote: > Hi Krzysztof, > > On 3/7/23 03:42, Krzysztof Kozlowski wrote: >> On 06/03/2023 20:15, Sean Anderson wrote: >>> This is a generic binding for simple MMIO GPIO controllers. Although we >>> have a single driver for these controllers, they were previously spread >>> over several files. Consolidate them. The register descriptions are >>> adapted from the comments in the source. There is no set order for the >>> registers, so I have not specified one. >>> >>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>> --- >>> >>> Changes in v10: >>> - New >>> >>> .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- >>> .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ >>> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- >>> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- >>> 4 files changed, 137 insertions(+), 91 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >>> delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt >>> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt >> >> https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/ > > Thanks for linking to that. > > I believe this patch should be applied instead of that one because > > - It documents all the registers, which were previously only documented > in the driver > - It handles the endianness properties. > - It consolidates the various descriptions of this binding into one > schema. Sure, sounds reasonable. You can just quickly check if my other comments apply here as well (but seems not): https://lore.kernel.org/all/4df3ec7a-e4af-89bc-9eda-21150395a935@linaro.org/ Best regards, Krzysztof
On Mon, Mar 06, 2023 at 02:15:25PM -0500, Sean Anderson wrote: > This is a generic binding for simple MMIO GPIO controllers. Although we > have a single driver for these controllers, they were previously spread > over several files. Consolidate them. The register descriptions are > adapted from the comments in the source. There is no set order for the > registers, so I have not specified one. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v10: > - New > > .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- > .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ > .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- > .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- > 4 files changed, 137 insertions(+), 91 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > index 4d69f79df859..e11f4af49c52 100644 > --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > @@ -4,7 +4,7 @@ > $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Broadcom BCM6345 GPIO controller > +title: Broadcom BCM63xx GPIO controller > > maintainers: > - Álvaro Fernández Rojas <noltari@gmail.com> > @@ -18,8 +18,6 @@ description: |+ > > BCM6338 have 8-bit data and dirout registers, where GPIO state can be read > and/or written, and the direction changed from input to output. > - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read > - and/or written, and the direction changed from input to output. > BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data > and dirout registers, where GPIO state can be read and/or written, and the > direction changed from input to output. > @@ -29,7 +27,6 @@ properties: > enum: > - brcm,bcm6318-gpio > - brcm,bcm6328-gpio > - - brcm,bcm6345-gpio > - brcm,bcm6358-gpio > - brcm,bcm6362-gpio > - brcm,bcm6368-gpio > @@ -63,17 +60,6 @@ required: > additionalProperties: false > > examples: > - - | > - gpio@fffe0406 { > - compatible = "brcm,bcm6345-gpio"; > - reg-names = "dirout", "dat"; > - reg = <0xfffe0406 2>, <0xfffe040a 2>; > - native-endian; > - > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - | > gpio@0 { > compatible = "brcm,bcm63268-gpio"; > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > new file mode 100644 > index 000000000000..fd5c7055d542 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Generic MMIO GPIO > + > +maintainers: > + - Linus Walleij <linus.walleij@linaro.org> > + - Bartosz Golaszewski <brgl@bgdev.pl> > + > +description: | Don't need '|' unless you want line endings preserved. Elsewhere too. > + Some simple GPIO controllers may consist of a single data register or a pair > + of set/clear-bit registers. Such controllers are common for glue logic in > + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped > + NAND-style parallel busses. > + > +properties: > + big-endian: > + true big-endian: true > + > + compatible: > + enum: > + - brcm,bcm6345-gpio # Broadcom BCM6345 GPIO controller > + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller > + - ni,169445-nand-gpio # National Instruments 169445 GPIO NAND controller > + > + '#gpio-cells': > + const: 2 > + > + gpio-controller: > + true ditto. > + > + reg: > + minItems: 1 > + description: | > + A list of registers in the controller. The width of each register is > + determined by its size. All registers must have the same width. The number > + of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. > + items: > + - description: | > + Register to READ the value of the GPIO lines. If GPIO line is high, > + the bit will be set. If the GPIO line is low, the bit will be cleared. > + This register may also be used to drive GPIOs if the SET register is > + omitted. > + - description: | > + Register to SET the value of the GPIO lines. Setting a bit in this > + register will drive the GPIO line high. > + - description: | > + Register to CLEAR the value of the GPIO lines. Setting a bit in this > + register will drive the GPIO line low. If this register is omitted, > + the SET register will be used to clear the GPIO lines as well, by > + actively writing the line with 0. > + - description: | > + Register to set the line as OUTPUT. Setting a bit in this register > + will turn that line into an output line. Conversely, clearing a bit > + will turn that line into an input. > + - description: | > + Register to set this line as INPUT. Setting a bit in this register > + will turn that line into an input line. Conversely, clearing a bit > + will turn that line into an output. > + > + reg-names: > + minItems: 1 > + maxItems: 5 > + items: > + enum: > + - dat > + - set > + - clr > + - dirout > + - dirin > + > + native-endian: > + true > + > + no-output: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + If this property is present, the controller cannot drive the GPIO lines. > + > +required: > + - compatible > + - reg > + - reg-names > + - '#gpio-cells' > + - gpio-controller > + > +additionalProperties: false > + > +examples: > + - | > + nand-gpio-out@1f300010 { Use generic node name: gpio@... > + compatible = "ni,169445-nand-gpio"; > + reg = <0x1f300010 0x4>; > + reg-names = "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + nand-gpio-in@1f300014 { > + compatible = "ni,169445-nand-gpio"; > + reg = <0x1f300014 0x4>; > + reg-names = "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + no-output; > + }; > + > + gpio0@e0000000 { > + compatible = "wd,mbl-gpio"; > + reg-names = "dat"; > + reg = <0xe0000000 0x1>; > + #gpio-cells = <2>; > + gpio-controller; > + }; > + > + gpio1@e0100000 { > + compatible = "wd,mbl-gpio"; > + reg-names = "dat"; > + reg = <0xe0100000 0x1>; > + #gpio-cells = <2>; > + gpio-controller; > + no-output; > + }; > + > + gpio@fffe0406 { > + compatible = "brcm,bcm6345-gpio"; > + reg-names = "dirout", "dat"; > + reg = <0xfffe0406 2>, <0xfffe040a 2>; > + native-endian; > + > + gpio-controller; > + #gpio-cells = <2>; > + }; > diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > deleted file mode 100644 > index ca2f8c745a27..000000000000 > --- a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -Bindings for the National Instruments 169445 GPIO NAND controller > - > -The 169445 GPIO NAND controller has two memory mapped GPIO registers, one > -for input (the ready signal) and one for output (control signals). It is > -intended to be used with the GPIO NAND driver. > - > -Required properties: > - - compatible: should be "ni,169445-nand-gpio" > - - reg-names: must contain > - "dat" - data register > - - reg: address + size pairs describing the GPIO register sets; > - order must correspond with the order of entries in reg-names > - - #gpio-cells: must be set to 2. The first cell is the pin number and > - the second cell is used to specify the gpio polarity: > - 0 = active high > - 1 = active low > - - gpio-controller: Marks the device node as a gpio controller. > - > -Optional properties: > - - no-output: disables driving output on the pins > - > -Examples: > - gpio1: nand-gpio-out@1f300010 { > - compatible = "ni,169445-nand-gpio"; > - reg = <0x1f300010 0x4>; > - reg-names = "dat"; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio2: nand-gpio-in@1f300014 { > - compatible = "ni,169445-nand-gpio"; > - reg = <0x1f300014 0x4>; > - reg-names = "dat"; > - gpio-controller; > - #gpio-cells = <2>; > - no-output; > - }; > diff --git a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt b/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > deleted file mode 100644 > index 038c3a6a1f4d..000000000000 > --- a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. > - > -The Western Digital MyBook Live has two memory-mapped GPIO controllers. > -Both GPIO controller only have a single 8-bit data register, where GPIO > -state can be read and/or written. > - > -Required properties: > - - compatible: should be "wd,mbl-gpio" > - - reg-names: must contain > - "dat" - data register > - - reg: address + size pairs describing the GPIO register sets; > - order must correspond with the order of entries in reg-names > - - #gpio-cells: must be set to 2. The first cell is the pin number and > - the second cell is used to specify the gpio polarity: > - 0 = active high > - 1 = active low > - - gpio-controller: Marks the device node as a gpio controller. > - > -Optional properties: > - - no-output: GPIOs are read-only. > - > -Examples: > - gpio0: gpio0@e0000000 { > - compatible = "wd,mbl-gpio"; > - reg-names = "dat"; > - reg = <0xe0000000 0x1>; > - #gpio-cells = <2>; > - gpio-controller; > - }; > - > - gpio1: gpio1@e0100000 { > - compatible = "wd,mbl-gpio"; > - reg-names = "dat"; > - reg = <0xe0100000 0x1>; > - #gpio-cells = <2>; > - gpio-controller; > - no-output; > - }; > -- > 2.35.1.1320.gc452695387.dirty >
On Tue, Mar 7, 2023 at 4:35 PM Sean Anderson <sean.anderson@seco.com> wrote: > On 3/7/23 03:42, Krzysztof Kozlowski wrote: > > https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/ > > Thanks for linking to that. > > I believe this patch should be applied instead of that one because > > - It documents all the registers, which were previously only documented > in the driver > - It handles the endianness properties. > - It consolidates the various descriptions of this binding into one > schema. Niall are you sending a v3 of this patch soon? Include Sean on the reviewer list! Yours, Linus Walleij
On 3/8/23 18:10, Rob Herring wrote: > On Mon, Mar 06, 2023 at 02:15:25PM -0500, Sean Anderson wrote: >> This is a generic binding for simple MMIO GPIO controllers. Although we >> have a single driver for these controllers, they were previously spread >> over several files. Consolidate them. The register descriptions are >> adapted from the comments in the source. There is no set order for the >> registers, so I have not specified one. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v10: >> - New >> >> .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- >> .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ >> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- >> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- >> 4 files changed, 137 insertions(+), 91 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >> delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt >> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt >> >> diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml >> index 4d69f79df859..e11f4af49c52 100644 >> --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml >> +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml >> @@ -4,7 +4,7 @@ >> $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# >> $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> -title: Broadcom BCM6345 GPIO controller >> +title: Broadcom BCM63xx GPIO controller >> >> maintainers: >> - Álvaro Fernández Rojas <noltari@gmail.com> >> @@ -18,8 +18,6 @@ description: |+ >> >> BCM6338 have 8-bit data and dirout registers, where GPIO state can be read >> and/or written, and the direction changed from input to output. >> - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read >> - and/or written, and the direction changed from input to output. >> BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data >> and dirout registers, where GPIO state can be read and/or written, and the >> direction changed from input to output. >> @@ -29,7 +27,6 @@ properties: >> enum: >> - brcm,bcm6318-gpio >> - brcm,bcm6328-gpio >> - - brcm,bcm6345-gpio >> - brcm,bcm6358-gpio >> - brcm,bcm6362-gpio >> - brcm,bcm6368-gpio >> @@ -63,17 +60,6 @@ required: >> additionalProperties: false >> >> examples: >> - - | >> - gpio@fffe0406 { >> - compatible = "brcm,bcm6345-gpio"; >> - reg-names = "dirout", "dat"; >> - reg = <0xfffe0406 2>, <0xfffe040a 2>; >> - native-endian; >> - >> - gpio-controller; >> - #gpio-cells = <2>; >> - }; >> - >> - | >> gpio@0 { >> compatible = "brcm,bcm63268-gpio"; >> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >> new file mode 100644 >> index 000000000000..fd5c7055d542 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml >> @@ -0,0 +1,136 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Generic MMIO GPIO >> + >> +maintainers: >> + - Linus Walleij <linus.walleij@linaro.org> >> + - Bartosz Golaszewski <brgl@bgdev.pl> >> + >> +description: | > > Don't need '|' unless you want line endings preserved. Elsewhere too. OK >> + Some simple GPIO controllers may consist of a single data register or a pair >> + of set/clear-bit registers. Such controllers are common for glue logic in >> + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped >> + NAND-style parallel busses. >> + >> +properties: >> + big-endian: >> + true > > big-endian: true OK >> + >> + compatible: >> + enum: >> + - brcm,bcm6345-gpio # Broadcom BCM6345 GPIO controller >> + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller >> + - ni,169445-nand-gpio # National Instruments 169445 GPIO NAND controller >> + >> + '#gpio-cells': >> + const: 2 >> + >> + gpio-controller: >> + true > > ditto. OK --Sean
On Mon, 6 Mar 2023 at 22:27, Sean Anderson <sean.anderson@seco.com> wrote: > > On 3/6/23 15:51, Jonas Gorski wrote: > > Hi, > > > > On Mon, 6 Mar 2023 at 20:16, Sean Anderson <sean.anderson@seco.com> wrote: > >> > >> This is a generic binding for simple MMIO GPIO controllers. Although we > >> have a single driver for these controllers, they were previously spread > >> over several files. Consolidate them. The register descriptions are > >> adapted from the comments in the source. There is no set order for the > >> registers, so I have not specified one. > >> > >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> > >> --- > >> > >> Changes in v10: > >> - New > >> > >> .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- > >> .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ > >> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- > >> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- > >> 4 files changed, 137 insertions(+), 91 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > >> delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > >> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > >> > >> diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > >> index 4d69f79df859..e11f4af49c52 100644 > >> --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > >> +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > > > > You are (re-)moving the compatible this file is named after, you might > > want to rename the file as well then. Going by age bcm6358 would be > > the next oldest one (bcm6318 would be the newest, despite the lowest > > number). > > I can do that. Would it be fine to rename to e.g. brcm,bcm63xx-gpio.yaml? I'm not up to date with current naming policies (if there are any at all), but looking at what's currently there this should be fine. Jonas
On 09/03/2023 09:16, Linus Walleij wrote: > *External Message* - Use caution before opening links or attachments > > On Tue, Mar 7, 2023 at 4:35 PM Sean Anderson <sean.anderson@seco.com> wrote: >> On 3/7/23 03:42, Krzysztof Kozlowski wrote: > >>> https://urldefense.com/v3/__https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/__;!!In4Qlw!uQKGkt7dO5TA-561XcuPNoqyti_AogqJ0cV3ymFZNob-Q1-Z1xmcOv_22JBP5xO-OIemaCZ1VY37nWLIe1AXyOkieg$ >> >> Thanks for linking to that. >> >> I believe this patch should be applied instead of that one because >> >> - It documents all the registers, which were previously only documented >> in the driver >> - It handles the endianness properties. >> - It consolidates the various descriptions of this binding into one >> schema. > > Niall are you sending a v3 of this patch soon? > Include Sean on the reviewer list! > > Yours, > Linus Walleij I never got around to working on the V3 patch. The hold up for me was the changes to the bindings. I'm now wondering if I should wait on Sean's patch being accepted and then I could re-submit the driver changes. What's the consensus ? Regards, Niall.
On 3/13/23 04:53, Leonard, Niall wrote: > [You don't often get email from niall.leonard@ncr.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > On 09/03/2023 09:16, Linus Walleij wrote: >> *External Message* - Use caution before opening links or attachments >> >> On Tue, Mar 7, 2023 at 4:35 PM Sean Anderson <sean.anderson@seco.com> wrote: >>> On 3/7/23 03:42, Krzysztof Kozlowski wrote: >> >>>> https://urldefense.com/v3/__https://lore.kernel.org/all/20230126-gpio-mmio-fix-v2-1-38397aace340@ncr.com/__;!!In4Qlw!uQKGkt7dO5TA-561XcuPNoqyti_AogqJ0cV3ymFZNob-Q1-Z1xmcOv_22JBP5xO-OIemaCZ1VY37nWLIe1AXyOkieg$ >>> >>> Thanks for linking to that. >>> >>> I believe this patch should be applied instead of that one because >>> >>> - It documents all the registers, which were previously only documented >>> in the driver >>> - It handles the endianness properties. >>> - It consolidates the various descriptions of this binding into one >>> schema. >> >> Niall are you sending a v3 of this patch soon? >> Include Sean on the reviewer list! >> >> Yours, >> Linus Walleij > I never got around to working on the V3 patch. The hold up for me was > the changes to the bindings. > I'm now wondering if I should wait on Sean's patch being accepted and > then I could re-submit the driver changes. > What's the consensus ? I am going to submit v11 later today. However, the phy subsystem maintainer refuses to review the phy patches until all the other patches are ready. Therefore, I suspect v11 may not be the last revision of this series. If the GPIO folks want to pick v11 of this patch separately, I think that would help accelerate the process. --Sean
On Mon, Mar 13, 2023 at 9:53 AM Leonard, Niall <Niall.Leonard@ncr.com> wrote: > > Niall are you sending a v3 of this patch soon? > > Include Sean on the reviewer list! > I never got around to working on the V3 patch. The hold up for me was > the changes to the bindings. > I'm now wondering if I should wait on Sean's patch being accepted and > then I could re-submit the driver changes. > What's the consensus ? Sean picked it up for shepherding, it looks very good, as soon as the DT maintainers give it a nod Bartosz can merge it. Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml index 4d69f79df859..e11f4af49c52 100644 --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6345 GPIO controller +title: Broadcom BCM63xx GPIO controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> @@ -18,8 +18,6 @@ description: |+ BCM6338 have 8-bit data and dirout registers, where GPIO state can be read and/or written, and the direction changed from input to output. - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read - and/or written, and the direction changed from input to output. BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data and dirout registers, where GPIO state can be read and/or written, and the direction changed from input to output. @@ -29,7 +27,6 @@ properties: enum: - brcm,bcm6318-gpio - brcm,bcm6328-gpio - - brcm,bcm6345-gpio - brcm,bcm6358-gpio - brcm,bcm6362-gpio - brcm,bcm6368-gpio @@ -63,17 +60,6 @@ required: additionalProperties: false examples: - - | - gpio@fffe0406 { - compatible = "brcm,bcm6345-gpio"; - reg-names = "dirout", "dat"; - reg = <0xfffe0406 2>, <0xfffe040a 2>; - native-endian; - - gpio-controller; - #gpio-cells = <2>; - }; - - | gpio@0 { compatible = "brcm,bcm63268-gpio"; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml new file mode 100644 index 000000000000..fd5c7055d542 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic MMIO GPIO + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + - Bartosz Golaszewski <brgl@bgdev.pl> + +description: | + Some simple GPIO controllers may consist of a single data register or a pair + of set/clear-bit registers. Such controllers are common for glue logic in + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped + NAND-style parallel busses. + +properties: + big-endian: + true + + compatible: + enum: + - brcm,bcm6345-gpio # Broadcom BCM6345 GPIO controller + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + - ni,169445-nand-gpio # National Instruments 169445 GPIO NAND controller + + '#gpio-cells': + const: 2 + + gpio-controller: + true + + reg: + minItems: 1 + description: | + A list of registers in the controller. The width of each register is + determined by its size. All registers must have the same width. The number + of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. + items: + - description: | + Register to READ the value of the GPIO lines. If GPIO line is high, + the bit will be set. If the GPIO line is low, the bit will be cleared. + This register may also be used to drive GPIOs if the SET register is + omitted. + - description: | + Register to SET the value of the GPIO lines. Setting a bit in this + register will drive the GPIO line high. + - description: | + Register to CLEAR the value of the GPIO lines. Setting a bit in this + register will drive the GPIO line low. If this register is omitted, + the SET register will be used to clear the GPIO lines as well, by + actively writing the line with 0. + - description: | + Register to set the line as OUTPUT. Setting a bit in this register + will turn that line into an output line. Conversely, clearing a bit + will turn that line into an input. + - description: | + Register to set this line as INPUT. Setting a bit in this register + will turn that line into an input line. Conversely, clearing a bit + will turn that line into an output. + + reg-names: + minItems: 1 + maxItems: 5 + items: + enum: + - dat + - set + - clr + - dirout + - dirin + + native-endian: + true + + no-output: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If this property is present, the controller cannot drive the GPIO lines. + +required: + - compatible + - reg + - reg-names + - '#gpio-cells' + - gpio-controller + +additionalProperties: false + +examples: + - | + nand-gpio-out@1f300010 { + compatible = "ni,169445-nand-gpio"; + reg = <0x1f300010 0x4>; + reg-names = "dat"; + gpio-controller; + #gpio-cells = <2>; + }; + + nand-gpio-in@1f300014 { + compatible = "ni,169445-nand-gpio"; + reg = <0x1f300014 0x4>; + reg-names = "dat"; + gpio-controller; + #gpio-cells = <2>; + no-output; + }; + + gpio0@e0000000 { + compatible = "wd,mbl-gpio"; + reg-names = "dat"; + reg = <0xe0000000 0x1>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio1@e0100000 { + compatible = "wd,mbl-gpio"; + reg-names = "dat"; + reg = <0xe0100000 0x1>; + #gpio-cells = <2>; + gpio-controller; + no-output; + }; + + gpio@fffe0406 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; + reg = <0xfffe0406 2>, <0xfffe040a 2>; + native-endian; + + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt deleted file mode 100644 index ca2f8c745a27..000000000000 --- a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the National Instruments 169445 GPIO NAND controller - -The 169445 GPIO NAND controller has two memory mapped GPIO registers, one -for input (the ready signal) and one for output (control signals). It is -intended to be used with the GPIO NAND driver. - -Required properties: - - compatible: should be "ni,169445-nand-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: disables driving output on the pins - -Examples: - gpio1: nand-gpio-out@1f300010 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300010 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: nand-gpio-in@1f300014 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300014 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - no-output; - }; diff --git a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt b/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt deleted file mode 100644 index 038c3a6a1f4d..000000000000 --- a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. - -The Western Digital MyBook Live has two memory-mapped GPIO controllers. -Both GPIO controller only have a single 8-bit data register, where GPIO -state can be read and/or written. - -Required properties: - - compatible: should be "wd,mbl-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: GPIOs are read-only. - -Examples: - gpio0: gpio0@e0000000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0000000 0x1>; - #gpio-cells = <2>; - gpio-controller; - }; - - gpio1: gpio1@e0100000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0100000 0x1>; - #gpio-cells = <2>; - gpio-controller; - no-output; - };
This is a generic binding for simple MMIO GPIO controllers. Although we have a single driver for these controllers, they were previously spread over several files. Consolidate them. The register descriptions are adapted from the comments in the source. There is no set order for the registers, so I have not specified one. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- Changes in v10: - New .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- 4 files changed, 137 insertions(+), 91 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt