| Message ID | 20230215010717.3612794-7-rananta@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for vPMU selftests | expand |
Hi Raghu, On Tue, Feb 14, 2023 at 5:07 PM Raghavendra Rao Ananta <rananta@google.com> wrote: > > Add the definitions of ARMV8_PMU_CNTOVS_C (Cycle counter overflow > bit) for overflow status registers and ARMV8_PMU_CNTENSET_C (Cycle > counter enable bit) for PMCNTENSET_EL0 register. > > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> > --- > tools/arch/arm64/include/asm/perf_event.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/tools/arch/arm64/include/asm/perf_event.h b/tools/arch/arm64/include/asm/perf_event.h > index 97e49a4d4969f..8ce23aabf6fe6 100644 > --- a/tools/arch/arm64/include/asm/perf_event.h > +++ b/tools/arch/arm64/include/asm/perf_event.h > @@ -222,9 +222,11 @@ > /* > * PMOVSR: counters overflow flag status reg > */ > +#define ARMV8_PMU_CNTOVS_C (1 << 31) /* Cycle counter overflow bit */ Nit: This macro doesn't seem to be used in any of the patches. Do we need this ? Thank you, Reiji > #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ > #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK > > + > /* > * PMXEVTYPER: Event selection reg > */ > @@ -247,6 +249,11 @@ > #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ > #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ > > +/* > + * PMCNTENSET: Count Enable set reg > + */ > +#define ARMV8_PMU_CNTENSET_C (1 << 31) /* Cycle counter enable bit */ > + > /* PMMIR_EL1.SLOTS mask */ > #define ARMV8_PMU_SLOTS_MASK 0xff > > -- > 2.39.1.581.gbfd45094c4-goog >
Hi Reiji, On Thu, Mar 2, 2023 at 4:47 PM Reiji Watanabe <reijiw@google.com> wrote: > > Hi Raghu, > > On Tue, Feb 14, 2023 at 5:07 PM Raghavendra Rao Ananta > <rananta@google.com> wrote: > > > > Add the definitions of ARMV8_PMU_CNTOVS_C (Cycle counter overflow > > bit) for overflow status registers and ARMV8_PMU_CNTENSET_C (Cycle > > counter enable bit) for PMCNTENSET_EL0 register. > > > > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> > > --- > > tools/arch/arm64/include/asm/perf_event.h | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/tools/arch/arm64/include/asm/perf_event.h b/tools/arch/arm64/include/asm/perf_event.h > > index 97e49a4d4969f..8ce23aabf6fe6 100644 > > --- a/tools/arch/arm64/include/asm/perf_event.h > > +++ b/tools/arch/arm64/include/asm/perf_event.h > > @@ -222,9 +222,11 @@ > > /* > > * PMOVSR: counters overflow flag status reg > > */ > > +#define ARMV8_PMU_CNTOVS_C (1 << 31) /* Cycle counter overflow bit */ > > Nit: This macro doesn't seem to be used in any of the patches. > Do we need this ? > Ah, I think originally I intended to use this instead of defining my own ARMV8_PMU_CYCLE_COUNTER_IDX to align with other pmc idx-es. But I think the latter is better. I'll remove ARMV8_PMU_CNTOVS_C. Thank you. Raghavendra > Thank you, > Reiji > > > > #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ > > #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK > > > > + > > /* > > * PMXEVTYPER: Event selection reg > > */ > > @@ -247,6 +249,11 @@ > > #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ > > #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ > > > > +/* > > + * PMCNTENSET: Count Enable set reg > > + */ > > +#define ARMV8_PMU_CNTENSET_C (1 << 31) /* Cycle counter enable bit */ > > + > > /* PMMIR_EL1.SLOTS mask */ > > #define ARMV8_PMU_SLOTS_MASK 0xff > > > > -- > > 2.39.1.581.gbfd45094c4-goog > >
diff --git a/tools/arch/arm64/include/asm/perf_event.h b/tools/arch/arm64/include/asm/perf_event.h index 97e49a4d4969f..8ce23aabf6fe6 100644 --- a/tools/arch/arm64/include/asm/perf_event.h +++ b/tools/arch/arm64/include/asm/perf_event.h @@ -222,9 +222,11 @@ /* * PMOVSR: counters overflow flag status reg */ +#define ARMV8_PMU_CNTOVS_C (1 << 31) /* Cycle counter overflow bit */ #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK + /* * PMXEVTYPER: Event selection reg */ @@ -247,6 +249,11 @@ #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ +/* + * PMCNTENSET: Count Enable set reg + */ +#define ARMV8_PMU_CNTENSET_C (1 << 31) /* Cycle counter enable bit */ + /* PMMIR_EL1.SLOTS mask */ #define ARMV8_PMU_SLOTS_MASK 0xff
Add the definitions of ARMV8_PMU_CNTOVS_C (Cycle counter overflow bit) for overflow status registers and ARMV8_PMU_CNTENSET_C (Cycle counter enable bit) for PMCNTENSET_EL0 register. Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> --- tools/arch/arm64/include/asm/perf_event.h | 7 +++++++ 1 file changed, 7 insertions(+)