| Message ID | 20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | GMU-less A6xx support (A610, A619_holi) | expand |
On 14/03/2023 16:28, Konrad Dybcio wrote: > The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks > we'd normally assign to the GMU as if they were a part of the GMU, even > though they are not". It's a (good) software representation of the GMU_CX > and GMU_GX register spaces within the GPUSS that helps us programatically > treat these de-facto GMU-less parts in a way that's very similar to their > GMU-equipped cousins, massively saving up on code duplication. > > The "wrapper" register space was specifically designed to mimic the layout > of a real GMU, though it rather obviously does not have the M3 core et al. > > To sum it all up, the GMU wrapper is essentially a register space within > the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, > interrupts, multiple reg spaces, iommus and OPP. Document it. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------ > 1 file changed, 37 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml > index ab14e81cb050..021373e686e1 100644 > --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml > +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml > @@ -19,16 +19,18 @@ description: | > > properties: > compatible: > - items: > - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' > - - const: qcom,adreno-gmu > + oneOf: > + - items: > + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' > + - const: qcom,adreno-gmu > + - const: qcom,adreno-gmu-wrapper > > reg: > - minItems: 3 > + minItems: 1 > maxItems: 4 > > reg-names: > - minItems: 3 > + minItems: 1 > maxItems: 4 > > clocks: > @@ -44,7 +46,6 @@ properties: > - description: GMU HFI interrupt > - description: GMU interrupt > > - > interrupt-names: > items: > - const: hfi > @@ -72,14 +73,8 @@ required: > - compatible > - reg > - reg-names > - - clocks > - - clock-names > - - interrupts > - - interrupt-names > - power-domains > - power-domain-names > - - iommus > - - operating-points-v2 > > additionalProperties: false > > @@ -216,6 +211,27 @@ allOf: > - const: cxo > - const: axi > - const: memnoc Blank line (you added such between ifs in previous patch) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..021373e686e1 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - minItems: 3 + minItems: 1 maxItems: 4 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false @@ -216,6 +211,27 @@ allOf: - const: cxo - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 examples: - | @@ -249,3 +265,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + };
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------ 1 file changed, 37 insertions(+), 12 deletions(-)