| Message ID | 20230210114957.2667963-1-danishanwar@ti.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Introduce ICSSG based ethernet Driver | expand |
On Fri, 10 Feb 2023 17:19:55 +0530 MD Danish Anwar wrote: > This series depends on two patch series that are not yet merged, one in > the remoteproc tree and another in the soc tree. the first one is titled > Introduce PRU remoteproc consumer API and the second one is titled > Introduce PRU platform consumer API. > Both of these are required for this driver. > > To explain this dependency and to get reviews, I had earlier posted all > three of these as an RFC[1], this can be seen for understanding the > dependencies. And please continue to post them as RFC :( If there are dependencies which the networking tree doesn't have we can't possibly merge these :(
On Fri, Feb 10, 2023 at 05:19:57PM +0530, MD Danish Anwar wrote: > From: Roger Quadros <rogerq@ti.com> > > This is the Ethernet driver for TI AM654 Silicon rev. 2 > with the ICSSG PRU Sub-system running dual-EMAC firmware. > > The Programmable Real-time Unit and Industrial Communication Subsystem > Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI > SoCs. This subsystem is provided for the use cases like implementation of > custom peripheral interfaces, offloading of tasks from the other > processor cores of the SoC, etc. > > Every ICSSG core has two Programmable Real-Time Unit(PRUs), > two auxiliary Real-Time Transfer Unit (RT_PRUs), and > two Transmit Real-Time Transfer Units (TX_PRUs). Each one of these runs > its own firmware. Every ICSSG core has two MII ports connect to these > PRUs and also a MDIO port. > > The cores can run different firmwares to support different protocols and > features like switch-dev, timestamping, etc. > > It uses System DMA to transfer and receive packets and > shared memory register emulation between the firmware and > driver for control and configuration. > > This patch adds support for basic EMAC functionality with 1Gbps > and 100Mbps link speed. 10M and half duplex mode are not supported > currently as they require IEP, the support for which will be added later. > Support for switch-dev, timestamp, etc. will be added later > by subsequent patch series. > > Signed-off-by: Roger Quadros <rogerq@ti.com> > [Vignesh Raghavendra: add 10M full duplex support] > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > [Grygorii Strashko: add support for half duplex operation] > Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> > Signed-off-by: Puranjay Mohan <p-mohan@ti.com> > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> The PHY handling looks correct now. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
Hi Jakub, On 11/02/23 06:08, Jakub Kicinski wrote: > On Fri, 10 Feb 2023 17:19:55 +0530 MD Danish Anwar wrote: >> This series depends on two patch series that are not yet merged, one in >> the remoteproc tree and another in the soc tree. the first one is titled >> Introduce PRU remoteproc consumer API and the second one is titled >> Introduce PRU platform consumer API. >> Both of these are required for this driver. >> >> To explain this dependency and to get reviews, I had earlier posted all >> three of these as an RFC[1], this can be seen for understanding the >> dependencies. > > And please continue to post them as RFC :( If there are dependencies > which the networking tree doesn't have we can't possibly merge these :( Sure, I will post the next revision of this series as RFC. Once the dependencies are merged, I will send this series to networking tree so that this series can be merged.
Hi Am Fr., 10. Feb. 2023 um 13:02 Uhr schrieb MD Danish Anwar <danishanwar@ti.com>: > > The Programmable Real-time Unit and Industrial Communication Subsystem > Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI > SoCs. This subsystem is provided for the use cases like the implementation > of custom peripheral interfaces, offloading of tasks from the other > processor cores of the SoC, etc. > > The subsystem includes many accelerators for data processing like > multiplier and multiplier-accumulator. It also has peripherals like > UART, MII/RGMII, MDIO, etc. Every ICSSG core includes two 32-bit > load/store RISC CPU cores called PRUs. > > The above features allow it to be used for implementing custom firmware > based peripherals like ethernet. > > This series adds the YAML documentation and the driver with basic EMAC > support for TI AM654 Silicon Rev 2 SoC with the PRU_ICSSG Sub-system. > running dual-EMAC firmware. > This currently supports basic EMAC with 1Gbps and 100Mbps link. 10M and > half-duplex modes are not yet supported because they require the support > of an IEP, which will be added later. > Advanced features like switch-dev and timestamping will be added later. What are TI plans to support TI AM642 Silicon Rev 2?