| Message ID | 20230319160704.9858-2-frank@oltmanns.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fixing the DSI dot clock on Allwinner | expand |
Hi, On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote: > Set the required PLL rate by adjusting the dotclock rate when calling > clk_set_rate() when using DSI. > > According to the Allwinners A64's BSP code, a TCON divider of 4 has to > be used and the PLL rate needs to be set to the following frequency when > using DSI: > PLL rate = DCLK * bpp / lanes > > After this change the common mode set function would only contain > setting the resolution. Therefore, dissolve the function and transfer > the functionality to the individual mode set functions. > > Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> This is similar to: https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/ What's the story there? Maxime
Hi Maxime, On 2023-03-21 at 15:57:39 +0100, Maxime Ripard <maxime@cerno.tech> wrote: > Hi, > > On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote: >> Set the required PLL rate by adjusting the dotclock rate when calling >> clk_set_rate() when using DSI. >> >> According to the Allwinners A64’s BSP code, a TCON divider of 4 has to >> be used and the PLL rate needs to be set to the following frequency when >> using DSI: >> PLL rate = DCLK * bpp / lanes >> >> After this change the common mode set function would only contain >> setting the resolution. Therefore, dissolve the function and transfer >> the functionality to the individual mode set functions. >> >> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> > > This is similar to: > <https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/> > > What’s the story there? Sorry, as Roman wrote in the other thread, I submitted the patch after not hearing back from him for a week. My apologies, I wasn’t patient enough. So now there are two submissions to consider. FWIW, I think this patch is a bit more straightforward than the other one. Best regards, Frank > Maxime >
On Tue Mar 21, 2023 at 8:55 PM CET, Frank Oltmanns wrote:
> My apologies, I wasn’t patient enough.
Frank, there's no need to apologize, in my judgement. You weren't
impatient, we simply happened to run into a coordination problem for
which, I think, neither of us was particularly to blamew. Take it easy
:)
Roman
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 62b3538bd81f..02d52be42f06 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -323,18 +323,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, return delay; } -static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode) -{ - /* Configure the dot clock */ - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); - - /* Set the resolution */ - regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, - SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); -} - static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, const struct drm_connector *connector) { @@ -399,10 +387,24 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; + /* + * Configure the dot clock: + * For DSI the PLL rate has to respect the bits per pixel and + * number of lanes. + * + * According to the BSP code: + * TCON divider = 4 + * PLL rate = DCLK * bpp / lanes + */ tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 + * bpp / (lanes * SUN6I_DSI_TCON_DIV)); - sun4i_tcon0_mode_set_common(tcon, mode); + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -470,7 +472,14 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, tcon->dclk_min_div = 7; tcon->dclk_max_div = 7; - sun4i_tcon0_mode_set_common(tcon, mode); + + /* Configure the dot clock */ + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -549,7 +558,14 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, tcon->dclk_min_div = tcon->quirks->dclk_min_div; tcon->dclk_max_div = 127; - sun4i_tcon0_mode_set_common(tcon, mode); + + /* Configure the dot clock */ + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, connector);
Set the required PLL rate by adjusting the dotclock rate when calling clk_set_rate() when using DSI. According to the Allwinners A64's BSP code, a TCON divider of 4 has to be used and the PLL rate needs to be set to the following frequency when using DSI: PLL rate = DCLK * bpp / lanes After this change the common mode set function would only contain setting the resolution. Therefore, dissolve the function and transfer the functionality to the individual mode set functions. Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 15 deletions(-)