| Message ID | 20230322061856.2774840-1-suagrfillet@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [RFC] riscv: export cpu/freq invariant to scheduler | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | fail | Errors and warnings before: 18 this patch: 2307 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | fail | Errors and warnings before: 18 this patch: 17774 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Please don't use multiple blank lines WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Wed, Mar 22, 2023 at 02:18:56PM +0800, Song Shuai wrote: > RISC-V now manages CPU topology using arch_topology which provides > CPU capacity and frequency related interfaces to access the cpu/freq > invariant in possible heterogeneous or DVFS-enabled platforms. > > Here adds topology.h file to export the arch_topology interfaces for > replacing the scheduler's constant-based cpu/freq invariant accounting. > > Signed-off-by: Song Shuai <suagrfillet@gmail.com> > --- > arch/riscv/include/asm/topology.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 arch/riscv/include/asm/topology.h > > diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h > new file mode 100644 > index 000000000000..14bbd2472af6 > --- /dev/null > +++ b/arch/riscv/include/asm/topology.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_RISCV_TOPOLOGY_H > +#define __ASM_RISCV_TOPOLOGY_H riscv uses a single leading underscore. > + > +#include <linux/arch_topology.h> > + > +/* Replace task scheduler's default frequency-invariant accounting */ > +#define arch_scale_freq_tick topology_scale_freq_tick > +#define arch_set_freq_scale topology_set_freq_scale > +#define arch_scale_freq_capacity topology_get_freq_scale > +#define arch_scale_freq_invariant topology_scale_freq_invariant > + > +/* Replace task scheduler's default cpu-invariant accounting */ > +#define arch_scale_cpu_capacity topology_get_cpu_scale > +#define arch_update_cpu_topology topology_update_cpu_topology > + > + > +#include <asm-generic/topology.h> > +#endif /* __ASM_RISCV_TOPOLOGY_H */ > -- > 2.20.1 > This looks reasonable, at least from a "do what arm64 does" type of perspective. Why the RFC? Is it not tested? Also, if you repost, could please neaten it up a bit? Aligning all the defines would help and removing the extra blank line. Finally, why wasn't the "/* Enable topology flag updates */" comment also lifted from arm64 like the others? Thanks, drew
Andrew Jones <ajones@ventanamicro.com> 于2023年3月22日周三 08:03写道： > > On Wed, Mar 22, 2023 at 02:18:56PM +0800, Song Shuai wrote: > > RISC-V now manages CPU topology using arch_topology which provides > > CPU capacity and frequency related interfaces to access the cpu/freq > > invariant in possible heterogeneous or DVFS-enabled platforms. > > > > Here adds topology.h file to export the arch_topology interfaces for > > replacing the scheduler's constant-based cpu/freq invariant accounting. > > > > Signed-off-by: Song Shuai <suagrfillet@gmail.com> > > --- > > arch/riscv/include/asm/topology.h | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > create mode 100644 arch/riscv/include/asm/topology.h > > > > diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h > > new file mode 100644 > > index 000000000000..14bbd2472af6 > > --- /dev/null > > +++ b/arch/riscv/include/asm/topology.h > > @@ -0,0 +1,19 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __ASM_RISCV_TOPOLOGY_H > > +#define __ASM_RISCV_TOPOLOGY_H > > riscv uses a single leading underscore. ok. > > > + > > +#include <linux/arch_topology.h> > > + > > +/* Replace task scheduler's default frequency-invariant accounting */ > > +#define arch_scale_freq_tick topology_scale_freq_tick > > +#define arch_set_freq_scale topology_set_freq_scale > > +#define arch_scale_freq_capacity topology_get_freq_scale > > +#define arch_scale_freq_invariant topology_scale_freq_invariant > > + > > +/* Replace task scheduler's default cpu-invariant accounting */ > > +#define arch_scale_cpu_capacity topology_get_cpu_scale > > +#define arch_update_cpu_topology topology_update_cpu_topology > > + > > + > > +#include <asm-generic/topology.h> > > +#endif /* __ASM_RISCV_TOPOLOGY_H */ > > -- > > 2.20.1 > > > > This looks reasonable, at least from a "do what arm64 does" type of > perspective. Why the RFC? Is it not tested? I only tested it in the qemu sifive_u machine with a customed dtb not sure if it works in real hardware, so I posted it with RFC. > > Also, if you repost, could please neaten it up a bit? Aligning all > the defines would help and removing the extra blank line. Finally, > why wasn't the "/* Enable topology flag updates */" comment also > lifted from arm64 like the others? I'll add the comment back and tidy it up in the next post. > > Thanks, > drew
diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h new file mode 100644 index 000000000000..14bbd2472af6 --- /dev/null +++ b/arch/riscv/include/asm/topology.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_RISCV_TOPOLOGY_H +#define __ASM_RISCV_TOPOLOGY_H + +#include <linux/arch_topology.h> + +/* Replace task scheduler's default frequency-invariant accounting */ +#define arch_scale_freq_tick topology_scale_freq_tick +#define arch_set_freq_scale topology_set_freq_scale +#define arch_scale_freq_capacity topology_get_freq_scale +#define arch_scale_freq_invariant topology_scale_freq_invariant + +/* Replace task scheduler's default cpu-invariant accounting */ +#define arch_scale_cpu_capacity topology_get_cpu_scale +#define arch_update_cpu_topology topology_update_cpu_topology + + +#include <asm-generic/topology.h> +#endif /* __ASM_RISCV_TOPOLOGY_H */
RISC-V now manages CPU topology using arch_topology which provides CPU capacity and frequency related interfaces to access the cpu/freq invariant in possible heterogeneous or DVFS-enabled platforms. Here adds topology.h file to export the arch_topology interfaces for replacing the scheduler's constant-based cpu/freq invariant accounting. Signed-off-by: Song Shuai <suagrfillet@gmail.com> --- arch/riscv/include/asm/topology.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/riscv/include/asm/topology.h