| Message ID | 20230323022237.1807512-4-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/6] target/ppc: Fix width of some 32-bit SPRs | expand |
Nicholas Piggin <npiggin@gmail.com> writes: > This optional behavior was removed from the ISA in v3.0, see > Summary of Changes preface: > > Data Storage Interrupt Status Register for Alignment Interrupt: > Simplifies the Alignment interrupt by remov- ing the Data Storage > Interrupt Status Register (DSISR) from the set of registers modified > by the Alignment interrupt. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > target/ppc/excp_helper.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 5f0e363363..c8b8eca3b1 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) > break; > } > case POWERPC_EXCP_ALIGN: /* Alignment exception */ > - /* Get rS/rD and rA from faulting opcode */ > - /* > - * Note: the opcode fields will not be set properly for a > - * direct store load/store, but nobody cares as nobody > - * actually uses direct store segments. > - */ > - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; > + switch (env->excp_model) { Slightly better would be to check on (env->insn_flags2 & PPC2_ISA300). We were trying to phase out the usage of "exception models" wherever possible in favor of specific feature/isa level flags. > + case POWERPC_EXCP_970: > + case POWERPC_EXCP_POWER7: > + case POWERPC_EXCP_POWER8: > + /* Get rS/rD and rA from faulting opcode */ > + /* > + * Note: the opcode fields will not be set properly for a > + * direct store load/store, but nobody cares as nobody > + * actually uses direct store segments. > + */ > + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; > + break; > + default: > + /* Optional DSISR update was removed from ISA v3.0 */ > + break; > + } > break; > case POWERPC_EXCP_PROGRAM: /* Program exception */ > switch (env->error_code & ~0xF) {
On Fri Mar 24, 2023 at 11:39 PM AEST, Fabiano Rosas wrote: > Nicholas Piggin <npiggin@gmail.com> writes: > > > This optional behavior was removed from the ISA in v3.0, see > > Summary of Changes preface: > > > > Data Storage Interrupt Status Register for Alignment Interrupt: > > Simplifies the Alignment interrupt by remov- ing the Data Storage > > Interrupt Status Register (DSISR) from the set of registers modified > > by the Alignment interrupt. > > > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > --- > > target/ppc/excp_helper.c | 23 ++++++++++++++++------- > > 1 file changed, 16 insertions(+), 7 deletions(-) > > > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > > index 5f0e363363..c8b8eca3b1 100644 > > --- a/target/ppc/excp_helper.c > > +++ b/target/ppc/excp_helper.c > > @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) > > break; > > } > > case POWERPC_EXCP_ALIGN: /* Alignment exception */ > > - /* Get rS/rD and rA from faulting opcode */ > > - /* > > - * Note: the opcode fields will not be set properly for a > > - * direct store load/store, but nobody cares as nobody > > - * actually uses direct store segments. > > - */ > > - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; > > + switch (env->excp_model) { > > Slightly better would be to check on (env->insn_flags2 & PPC2_ISA300). > We were trying to phase out the usage of "exception models" wherever > possible in favor of specific feature/isa level flags. Oh good point, thanks for catching that. Will fix and resend the series (I've done the same thing in a few other places too). Thanks, Nick
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5f0e363363..c8b8eca3b1 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + switch (env->excp_model) { + case POWERPC_EXCP_970: + case POWERPC_EXCP_POWER7: + case POWERPC_EXCP_POWER8: + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + break; + default: + /* Optional DSISR update was removed from ISA v3.0 */ + break; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) {
This optional behavior was removed from the ISA in v3.0, see Summary of Changes preface: Data Storage Interrupt Status Register for Alignment Interrupt: Simplifies the Alignment interrupt by remov- ing the Data Storage Interrupt Status Register (DSISR) from the set of registers modified by the Alignment interrupt. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/excp_helper.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)