| Message ID | 20230327123433.896216-3-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Add Support for C10 chips | expand |
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote: > Add DP rates for Meteorlake. > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index da1c00ee92fb..4927aeb64f23 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp) > return 810000; > } > > +static int mtl_max_source_rate(struct intel_dp *intel_dp) > +{ > + return intel_dp_is_edp(intel_dp) ? 675000 : 810000; > +} > + > static int vbt_max_link_rate(struct intel_dp *intel_dp) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > @@ -444,6 +449,10 @@ static void > intel_dp_set_source_rates(struct intel_dp *intel_dp) > { > /* The values must be in increasing order */ > + static const int mtl_rates[] = { > + 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, > + 810000, > + }; > static const int icl_rates[] = { > 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, > 1000000, 1350000, > @@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) > drm_WARN_ON(&dev_priv->drm, > intel_dp->source_rates || intel_dp->num_source_rates); > > - if (DISPLAY_VER(dev_priv) >= 11) { > + if (DISPLAY_VER(dev_priv) >= 14) { > + source_rates = mtl_rates; > + size = ARRAY_SIZE(mtl_rates); > + max_rate = mtl_max_source_rate(intel_dp); > + } else if (DISPLAY_VER(dev_priv) >= 11) { > source_rates = icl_rates; > size = ARRAY_SIZE(icl_rates); > if (IS_DG2(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index da1c00ee92fb..4927aeb64f23 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp) return 810000; } +static int mtl_max_source_rate(struct intel_dp *intel_dp) +{ + return intel_dp_is_edp(intel_dp) ? 675000 : 810000; +} + static int vbt_max_link_rate(struct intel_dp *intel_dp) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; @@ -444,6 +449,10 @@ static void intel_dp_set_source_rates(struct intel_dp *intel_dp) { /* The values must be in increasing order */ + static const int mtl_rates[] = { + 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, + 810000, + }; static const int icl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 1000000, 1350000, @@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, intel_dp->source_rates || intel_dp->num_source_rates); - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(dev_priv) >= 14) { + source_rates = mtl_rates; + size = ARRAY_SIZE(mtl_rates); + max_rate = mtl_max_source_rate(intel_dp); + } else if (DISPLAY_VER(dev_priv) >= 11) { source_rates = icl_rates; size = ARRAY_SIZE(icl_rates); if (IS_DG2(dev_priv))