diff mbox series

[1/3] qtest: Add functions for accessing devices on Aspeed I2C controller

Message ID 20230327202416.3617162-2-stefanb@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series qtests: tpm: Add test cases for TPM TIS I2C device emulation | expand

Commit Message

Stefan Berger March 27, 2023, 8:24 p.m. UTC 
Add read and write functions for accessing registers of I2C devices
connected to the Aspeed I2C controller.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
 include/hw/i2c/aspeed_i2c.h |   7 +++
 tests/qtest/qtest_aspeed.c  | 109 ++++++++++++++++++++++++++++++++++++
 tests/qtest/qtest_aspeed.h  |  34 +++++++++++
 3 files changed, 150 insertions(+)
 create mode 100644 tests/qtest/qtest_aspeed.c
 create mode 100644 tests/qtest/qtest_aspeed.h

Comments

Cédric Le Goater March 28, 2023, 6:39 a.m. UTC | #1 
On 3/27/23 22:24, Stefan Berger wrote:
> Add read and write functions for accessing registers of I2C devices
> connected to the Aspeed I2C controller.
> 
> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

[... ]

> +#ifndef QTEST_ASPEED_H
> +#define QTEST_ASPEED_H
> +
> +#include <stdint.h>
> +
> +#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
> +
> +static inline uint32_t ast2600_aspeed_i2c_calc_dev_addr(uint8_t bus_num)

I think you could simplify the name ast2600_aspeed_i2c_calc_dev_addr()
to aspeed_i2c_calc_bus_addr() and add a comment saying it implements only
the AST2600 I2C controller. I don't think we will need the others.

> +{
> +    return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
> +}

The formula is :

    return soc_base + (soc_i2c_offset + bus_num) * soc_i2c_reg_size;

May be turn it that way in case you respin. This is minor.

Thanks,

C.
Stefan Berger March 28, 2023, 12:26 p.m. UTC | #2 
On 3/28/23 02:39, Cédric Le Goater wrote:
> On 3/27/23 22:24, Stefan Berger wrote:
>> Add read and write functions for accessing registers of I2C devices
>> connected to the Aspeed I2C controller.
>>
>> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
> 
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> 
> [... ]
> 
>> +#ifndef QTEST_ASPEED_H
>> +#define QTEST_ASPEED_H
>> +
>> +#include <stdint.h>
>> +
>> +#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
>> +
>> +static inline uint32_t ast2600_aspeed_i2c_calc_dev_addr(uint8_t bus_num)
> 
> I think you could simplify the name ast2600_aspeed_i2c_calc_dev_addr()
> to aspeed_i2c_calc_bus_addr() and add a comment saying it implements only
> the AST2600 I2C controller. I don't think we will need the others.


What are 'the others'?

> 
>> +{
>> +    return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
>> +}
> 
> The formula is :
> 
>     return soc_base + (soc_i2c_offset + bus_num) * soc_i2c_reg_size;

That's what I thought:

return soc_base + soc_i2c_offset + (bus_num * soc_i2c_reg_size);

I will keep it as it is, though.

     Stefan

> 
> May be turn it that way in case you respin. This is minor.
> 
> Thanks,
> 
> C.
>
Cédric Le Goater March 28, 2023, 1:10 p.m. UTC | #3 
On 3/28/23 14:26, Stefan Berger wrote:
> 
> 
> On 3/28/23 02:39, Cédric Le Goater wrote:
>> On 3/27/23 22:24, Stefan Berger wrote:
>>> Add read and write functions for accessing registers of I2C devices
>>> connected to the Aspeed I2C controller.
>>>
>>> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
>>
>> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>>
>> [... ]
>>
>>> +#ifndef QTEST_ASPEED_H
>>> +#define QTEST_ASPEED_H
>>> +
>>> +#include <stdint.h>
>>> +
>>> +#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
>>> +
>>> +static inline uint32_t ast2600_aspeed_i2c_calc_dev_addr(uint8_t bus_num)
>>
>> I think you could simplify the name ast2600_aspeed_i2c_calc_dev_addr()
>> to aspeed_i2c_calc_bus_addr() and add a comment saying it implements only
>> the AST2600 I2C controller. I don't think we will need the others.
> 
> 
> What are 'the others'?

AST2400 and AST2500 SoC.

>>> +{
>>> +    return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
>>> +}
>>
>> The formula is :
>>
>>     return soc_base + (soc_i2c_offset + bus_num) * soc_i2c_reg_size;
> 
> That's what I thought:
> 
> return soc_base + soc_i2c_offset + (bus_num * soc_i2c_reg_size);
>
> I will keep it as it is, though.

It should work also for the AST2600

FYI, see the layouts below,

Thanks,

C.


AST2400

     000000001e78a000-000000001e78afff (prio 0, i/o): aspeed.i2c
       000000001e78a040-000000001e78a07f (prio 0, i/o): aspeed.i2c.bus.0
       000000001e78a080-000000001e78a0bf (prio 0, i/o): aspeed.i2c.bus.1
       000000001e78a0c0-000000001e78a0ff (prio 0, i/o): aspeed.i2c.bus.2
       000000001e78a100-000000001e78a13f (prio 0, i/o): aspeed.i2c.bus.3
       000000001e78a140-000000001e78a17f (prio 0, i/o): aspeed.i2c.bus.4
       000000001e78a180-000000001e78a1bf (prio 0, i/o): aspeed.i2c.bus.5
       000000001e78a1c0-000000001e78a1ff (prio 0, i/o): aspeed.i2c.bus.6
       000000001e78a300-000000001e78a33f (prio 0, i/o): aspeed.i2c.bus.7
       000000001e78a340-000000001e78a37f (prio 0, i/o): aspeed.i2c.bus.8
       000000001e78a380-000000001e78a3bf (prio 0, i/o): aspeed.i2c.bus.9
       000000001e78a3c0-000000001e78a3ff (prio 0, i/o): aspeed.i2c.bus.10
       000000001e78a400-000000001e78a43f (prio 0, i/o): aspeed.i2c.bus.11
       000000001e78a440-000000001e78a47f (prio 0, i/o): aspeed.i2c.bus.12
       000000001e78a480-000000001e78a4bf (prio 0, i/o): aspeed.i2c.bus.13
       000000001e78a800-000000001e78afff (prio 0, i/o): aspeed.i2c-pool

AST2500

     000000001e78a000-000000001e78afff (prio 0, i/o): aspeed.i2c
       000000001e78a040-000000001e78a07f (prio 0, i/o): aspeed.i2c.bus.0
       000000001e78a080-000000001e78a0bf (prio 0, i/o): aspeed.i2c.bus.1
       000000001e78a0c0-000000001e78a0ff (prio 0, i/o): aspeed.i2c.bus.2
       000000001e78a100-000000001e78a13f (prio 0, i/o): aspeed.i2c.bus.3
       000000001e78a140-000000001e78a17f (prio 0, i/o): aspeed.i2c.bus.4
       000000001e78a180-000000001e78a1bf (prio 0, i/o): aspeed.i2c.bus.5
       000000001e78a1c0-000000001e78a1ff (prio 0, i/o): aspeed.i2c.bus.6
       000000001e78a200-000000001e78a2ff (prio 0, i/o): aspeed.i2c-pool
       000000001e78a300-000000001e78a33f (prio 0, i/o): aspeed.i2c.bus.7
       000000001e78a340-000000001e78a37f (prio 0, i/o): aspeed.i2c.bus.8
       000000001e78a380-000000001e78a3bf (prio 0, i/o): aspeed.i2c.bus.9
       000000001e78a3c0-000000001e78a3ff (prio 0, i/o): aspeed.i2c.bus.10
       000000001e78a400-000000001e78a43f (prio 0, i/o): aspeed.i2c.bus.11
       000000001e78a440-000000001e78a47f (prio 0, i/o): aspeed.i2c.bus.12
       000000001e78a480-000000001e78a4bf (prio 0, i/o): aspeed.i2c.bus.13

AST2600

     000000001e78a000-000000001e78afff (prio 0, i/o): aspeed.i2c
       000000001e78a080-000000001e78a0ff (prio 0, i/o): aspeed.i2c.bus.0
       000000001e78a100-000000001e78a17f (prio 0, i/o): aspeed.i2c.bus.1
       000000001e78a180-000000001e78a1ff (prio 0, i/o): aspeed.i2c.bus.2
       000000001e78a200-000000001e78a27f (prio 0, i/o): aspeed.i2c.bus.3
       000000001e78a280-000000001e78a2ff (prio 0, i/o): aspeed.i2c.bus.4
       000000001e78a300-000000001e78a37f (prio 0, i/o): aspeed.i2c.bus.5
       000000001e78a380-000000001e78a3ff (prio 0, i/o): aspeed.i2c.bus.6
       000000001e78a400-000000001e78a47f (prio 0, i/o): aspeed.i2c.bus.7
       000000001e78a480-000000001e78a4ff (prio 0, i/o): aspeed.i2c.bus.8
       000000001e78a500-000000001e78a57f (prio 0, i/o): aspeed.i2c.bus.9
       000000001e78a580-000000001e78a5ff (prio 0, i/o): aspeed.i2c.bus.10
       000000001e78a600-000000001e78a67f (prio 0, i/o): aspeed.i2c.bus.11
       000000001e78a680-000000001e78a6ff (prio 0, i/o): aspeed.i2c.bus.12
       000000001e78a700-000000001e78a77f (prio 0, i/o): aspeed.i2c.bus.13
       000000001e78a780-000000001e78a7ff (prio 0, i/o): aspeed.i2c.bus.14
       000000001e78a800-000000001e78a87f (prio 0, i/o): aspeed.i2c.bus.15
       000000001e78ac00-000000001e78adff (prio 0, i/o): aspeed.i2c-pool
Ninad Palsule March 28, 2023, 1:26 p.m. UTC | #4 
On 3/27/23 3:24 PM, Stefan Berger wrote:
> Add read and write functions for accessing registers of I2C devices
> connected to the Aspeed I2C controller.
>
> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>

> ---
>   include/hw/i2c/aspeed_i2c.h |   7 +++
>   tests/qtest/qtest_aspeed.c  | 109 ++++++++++++++++++++++++++++++++++++
>   tests/qtest/qtest_aspeed.h  |  34 +++++++++++
>   3 files changed, 150 insertions(+)
>   create mode 100644 tests/qtest/qtest_aspeed.c
>   create mode 100644 tests/qtest/qtest_aspeed.h
>
> diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
> index adc904d6c1..51c944efea 100644
> --- a/include/hw/i2c/aspeed_i2c.h
> +++ b/include/hw/i2c/aspeed_i2c.h
> @@ -38,6 +38,13 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
>   #define ASPEED_I2C_OLD_NUM_REG 11
>   #define ASPEED_I2C_NEW_NUM_REG 22
>   
> +#define A_I2CD_M_STOP_CMD       BIT(5)
> +#define A_I2CD_M_RX_CMD         BIT(3)
> +#define A_I2CD_M_TX_CMD         BIT(1)
> +#define A_I2CD_M_START_CMD      BIT(0)
> +
> +#define A_I2CD_MASTER_EN        BIT(0)
> +
>   /* Tx State Machine */
>   #define   I2CD_TX_STATE_MASK                  0xf
>   #define     I2CD_IDLE                         0x0
> diff --git a/tests/qtest/qtest_aspeed.c b/tests/qtest/qtest_aspeed.c
> new file mode 100644
> index 0000000000..2fcafc22fc
> --- /dev/null
> +++ b/tests/qtest/qtest_aspeed.c
> @@ -0,0 +1,109 @@
> +/*
> + * Aspeed i2c bus interface for reading from and writing to i2c device registers
> + *
> + * Copyright (c) 2023 IBM Corporation
> + *
> + * Authors:
> + *   Stefan Berger <stefanb@linux.ibm.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qtest_aspeed.h"
> +#include "hw/i2c/aspeed_i2c.h"
> +#include "libqtest-single.h"
> +
> +static void aspeed_i2c_startup(uint32_t baseaddr, uint8_t slave_addr,
> +                               uint8_t reg)
> +{
> +    uint32_t v;
> +    static int once;
> +
> +    if (!once) {
> +        /* one time: enable master */
> +       writel(baseaddr + A_I2CC_FUN_CTRL, 0);
> +       v = readl(baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN;
> +       writel(baseaddr + A_I2CC_FUN_CTRL, v);
> +       once = 1;
> +    }
> +
> +    /* select device */
> +    writel(baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1);
> +    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD);
> +
> +    /* select the register to write to */
> +    writel(baseaddr + A_I2CD_BYTE_BUF, reg);
> +    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
> +}
> +
> +static uint32_t aspeed_i2c_read_n(uint32_t baseaddr, uint8_t slave_addr,
> +                                  uint8_t reg, size_t nbytes)
> +{
> +    uint32_t res = 0;
> +    uint32_t v;
> +    size_t i;
> +
> +    aspeed_i2c_startup(baseaddr, slave_addr, reg);
> +
> +    for (i = 0; i < nbytes; i++) {
> +        writel(baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD);
> +        v = readl(baseaddr + A_I2CD_BYTE_BUF) >> 8;
> +        res |= (v & 0xff) << (i * 8);
> +    }
> +
> +    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
> +
> +    return res;
> +}
> +
> +uint32_t aspeed_i2c_readl(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
> +{
> +    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint32_t));
> +}
> +
> +uint16_t aspeed_i2c_readw(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
> +{
> +    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint16_t));
> +}
> +
> +uint8_t aspeed_i2c_readb(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
> +{
> +    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint8_t));
> +}
> +
> +static void aspeed_i2c_write_n(uint32_t baseaddr, uint8_t slave_addr,
> +                               uint8_t reg, uint32_t v, size_t nbytes)
> +{
> +    size_t i;
> +
> +    aspeed_i2c_startup(baseaddr, slave_addr, reg);
> +
> +    for (i = 0; i < nbytes; i++) {
> +        writel(baseaddr + A_I2CD_BYTE_BUF, v & 0xff);
> +        v >>= 8;
> +        writel(baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
> +    }
> +
> +    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
> +}
> +
> +void aspeed_i2c_writel(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint32_t v)
> +{
> +    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
> +}
> +
> +void aspeed_i2c_writew(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint16_t v)
> +{
> +    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
> +}
> +
> +void aspeed_i2c_writeb(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint8_t v)
> +{
> +    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
> +}
> diff --git a/tests/qtest/qtest_aspeed.h b/tests/qtest/qtest_aspeed.h
> new file mode 100644
> index 0000000000..529061cf5b
> --- /dev/null
> +++ b/tests/qtest/qtest_aspeed.h
> @@ -0,0 +1,34 @@
> +/*
> + * Aspeed i2c bus interface to reading and writing to i2c device registers
> + *
> + * Copyright (c) 2023 IBM Corporation
> + *
> + * Authors:
> + *   Stefan Berger <stefanb@linux.ibm.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#ifndef QTEST_ASPEED_H
> +#define QTEST_ASPEED_H
> +
> +#include <stdint.h>
> +
> +#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
> +
> +static inline uint32_t ast2600_aspeed_i2c_calc_dev_addr(uint8_t bus_num)
> +{
> +    return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
> +}
> +
> +uint8_t aspeed_i2c_readb(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
> +uint16_t aspeed_i2c_readw(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
> +uint32_t aspeed_i2c_readl(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
> +void aspeed_i2c_writeb(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint8_t v);
> +void aspeed_i2c_writew(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint16_t v);
> +void aspeed_i2c_writel(uint32_t baseaddr, uint8_t slave_addr,
> +                       uint8_t reg, uint32_t v);
> +
> +#endif
diff mbox series

Patch

diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index adc904d6c1..51c944efea 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -38,6 +38,13 @@  OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
 #define ASPEED_I2C_OLD_NUM_REG 11
 #define ASPEED_I2C_NEW_NUM_REG 22
 
+#define A_I2CD_M_STOP_CMD       BIT(5)
+#define A_I2CD_M_RX_CMD         BIT(3)
+#define A_I2CD_M_TX_CMD         BIT(1)
+#define A_I2CD_M_START_CMD      BIT(0)
+
+#define A_I2CD_MASTER_EN        BIT(0)
+
 /* Tx State Machine */
 #define   I2CD_TX_STATE_MASK                  0xf
 #define     I2CD_IDLE                         0x0
diff --git a/tests/qtest/qtest_aspeed.c b/tests/qtest/qtest_aspeed.c
new file mode 100644
index 0000000000..2fcafc22fc
--- /dev/null
+++ b/tests/qtest/qtest_aspeed.c
@@ -0,0 +1,109 @@ 
+/*
+ * Aspeed i2c bus interface for reading from and writing to i2c device registers
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ *   Stefan Berger <stefanb@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qtest_aspeed.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "libqtest-single.h"
+
+static void aspeed_i2c_startup(uint32_t baseaddr, uint8_t slave_addr,
+                               uint8_t reg)
+{
+    uint32_t v;
+    static int once;
+
+    if (!once) {
+        /* one time: enable master */
+       writel(baseaddr + A_I2CC_FUN_CTRL, 0);
+       v = readl(baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN;
+       writel(baseaddr + A_I2CC_FUN_CTRL, v);
+       once = 1;
+    }
+
+    /* select device */
+    writel(baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1);
+    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD);
+
+    /* select the register to write to */
+    writel(baseaddr + A_I2CD_BYTE_BUF, reg);
+    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
+}
+
+static uint32_t aspeed_i2c_read_n(uint32_t baseaddr, uint8_t slave_addr,
+                                  uint8_t reg, size_t nbytes)
+{
+    uint32_t res = 0;
+    uint32_t v;
+    size_t i;
+
+    aspeed_i2c_startup(baseaddr, slave_addr, reg);
+
+    for (i = 0; i < nbytes; i++) {
+        writel(baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD);
+        v = readl(baseaddr + A_I2CD_BYTE_BUF) >> 8;
+        res |= (v & 0xff) << (i * 8);
+    }
+
+    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
+
+    return res;
+}
+
+uint32_t aspeed_i2c_readl(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint32_t));
+}
+
+uint16_t aspeed_i2c_readw(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint16_t));
+}
+
+uint8_t aspeed_i2c_readb(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
+{
+    return aspeed_i2c_read_n(baseaddr, slave_addr, reg, sizeof(uint8_t));
+}
+
+static void aspeed_i2c_write_n(uint32_t baseaddr, uint8_t slave_addr,
+                               uint8_t reg, uint32_t v, size_t nbytes)
+{
+    size_t i;
+
+    aspeed_i2c_startup(baseaddr, slave_addr, reg);
+
+    for (i = 0; i < nbytes; i++) {
+        writel(baseaddr + A_I2CD_BYTE_BUF, v & 0xff);
+        v >>= 8;
+        writel(baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
+    }
+
+    writel(baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
+}
+
+void aspeed_i2c_writel(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint32_t v)
+{
+    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
+}
+
+void aspeed_i2c_writew(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint16_t v)
+{
+    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
+}
+
+void aspeed_i2c_writeb(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint8_t v)
+{
+    aspeed_i2c_write_n(baseaddr, slave_addr, reg, v, sizeof(v));
+}
diff --git a/tests/qtest/qtest_aspeed.h b/tests/qtest/qtest_aspeed.h
new file mode 100644
index 0000000000..529061cf5b
--- /dev/null
+++ b/tests/qtest/qtest_aspeed.h
@@ -0,0 +1,34 @@ 
+/*
+ * Aspeed i2c bus interface to reading and writing to i2c device registers
+ *
+ * Copyright (c) 2023 IBM Corporation
+ *
+ * Authors:
+ *   Stefan Berger <stefanb@linux.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef QTEST_ASPEED_H
+#define QTEST_ASPEED_H
+
+#include <stdint.h>
+
+#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000
+
+static inline uint32_t ast2600_aspeed_i2c_calc_dev_addr(uint8_t bus_num)
+{
+    return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80;
+}
+
+uint8_t aspeed_i2c_readb(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+uint16_t aspeed_i2c_readw(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+uint32_t aspeed_i2c_readl(uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
+void aspeed_i2c_writeb(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint8_t v);
+void aspeed_i2c_writew(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint16_t v);
+void aspeed_i2c_writel(uint32_t baseaddr, uint8_t slave_addr,
+                       uint8_t reg, uint32_t v);
+
+#endif