| Message ID | 20230329111422.3693-1-mike.leach@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | perf: cs-etm: Update perf to handle new Coresight Trace ID | expand |
Arnaldo, On 29/03/2023 12:14, Mike Leach wrote: > The original method for allocating trace source ID values to sources was > to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). > The STM was allocated ID 0x1. > > This mechanism is broken for systems with more than 47 cores. > > The kernel related patches the provide a fixed Trace ID allocation mechanism > are now upstreamed. > > This patchset updates the perf code to handle the changes to the trace ID > notification mechanism that now uses the PERF_RECORD_AUX_OUTPUT_HW_ID > packet to set Trace ID in the perf ETM decoders. > > Applies to perf/core > > Changes since v7: > Split from original patchset [1] to be sent separately as kernel related > patches are now upstream. Please could you pull this in ? This is critical for enabling the CoreSight perf support on systems with > 47 cores. The kernel changes are already in. Suzuki > > [1] https://lore.kernel.org/linux-arm-kernel/20230116124928.5440-1-mike.leach@linaro.org/ > > Mike Leach (3): > perf: cs-etm: Move mapping of Trace ID and cpu into helper function > perf: cs-etm: Update record event to use new Trace ID protocol > perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet > > tools/include/linux/coresight-pmu.h | 47 ++- > tools/perf/arch/arm/util/cs-etm.c | 21 +- > .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + > tools/perf/util/cs-etm.c | 326 +++++++++++++++--- > tools/perf/util/cs-etm.h | 14 +- > 5 files changed, 350 insertions(+), 65 deletions(-) >