| Message ID | 20230203-evk-board-support-v3-16-0003e80e0095@baylibre.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Improve the MT8365 SoC and EVK board support | expand |
Il 29/03/23 10:54, amergnat@baylibre.com ha scritto: > From: Amjad Ouled-Ameur <aouledameur@baylibre.com> > > MT8365 has a SYST timer (System Timer), therefore the compatible node > should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer" > (which corresponds to ARM/ARM64 System Timer). > > Plus, register range should be 0x100 instead of 0x10. > > Finally, interrupt polarity of systimer is LEVEL_HIGH. > > Fix the above properties accordingly. > > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 29/03/2023 10:54, amergnat@baylibre.com wrote: > From: Amjad Ouled-Ameur <aouledameur@baylibre.com> > > MT8365 has a SYST timer (System Timer), therefore the compatible node > should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer" > (which corresponds to ARM/ARM64 System Timer). > > Plus, register range should be 0x100 instead of 0x10. > > Finally, interrupt polarity of systimer is LEVEL_HIGH. > > Fix the above properties accordingly. > > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Patch looks good but does not apply cleanly because of previous patches that I didn't take and need rework. Please resend the patches I didn't queue with the comments addressed. Regards, Matthias > --- > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index c3ea3cc97a47..959d8533c24c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -575,9 +575,9 @@ system_clk: dummy13m { > }; > > systimer: timer@10017000 { > - compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer"; > - reg = <0 0x10017000 0 0x10>; > - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; > + compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; > + reg = <0 0x10017000 0 0x100>; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&system_clk>; > clock-names = "clk13m"; > }; >
Hi Matthias Le jeu. 30 mars 2023 à 19:34, Matthias Brugger <matthias.bgg@gmail.com> a écrit : > > > > On 29/03/2023 10:54, amergnat@baylibre.com wrote: > > From: Amjad Ouled-Ameur <aouledameur@baylibre.com> > > > > MT8365 has a SYST timer (System Timer), therefore the compatible node > > should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer" > > (which corresponds to ARM/ARM64 System Timer). > > > > Plus, register range should be 0x100 instead of 0x10. > > > > Finally, interrupt polarity of systimer is LEVEL_HIGH. > > > > Fix the above properties accordingly. > > > > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > > Patch looks good but does not apply cleanly because of previous patches that I > didn't take and need rework. Please resend the patches I didn't queue with the > comments addressed. Sorry for that, I forgot to drop this patch since it has been already fixed in the Bero's series [1] I will drop it for the next version [1]: https://lore.kernel.org/all/20230309213501.794764-4-bero@baylibre.com/ Regards, Alex
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index c3ea3cc97a47..959d8533c24c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -575,9 +575,9 @@ system_clk: dummy13m { }; systimer: timer@10017000 { - compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer"; - reg = <0 0x10017000 0 0x10>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; + compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x100>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&system_clk>; clock-names = "clk13m"; };