| Message ID | 20230120172233.1905761-3-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/5] drm/msm/a6xx: Add support for A640 speed binning | expand |
On 20/01/2023 19:22, Konrad Dybcio wrote: > Add support for matching QFPROM fuse values to get the correct speed bin > on A650 (SM8250) GPUs. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Thank you for the patch. It took me a while to dive into various ways vendor kernels handle GPU speed bins. > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 0ee8cb3e490c..c5f5d0bb3fdc 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > +static u32 a650_get_speed_bin(u32 fuse) > +{ > + if (fuse == 0) > + return 0; > + else if (fuse == 1) > + return 1; > + else if (fuse == 2) > + return 2; > + else if (fuse == 3) > + return 3; > + > + return UINT_MAX; > +} > + > static u32 adreno_7c3_get_speed_bin(u32 fuse) > { > if (fuse == 0) > @@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) > val = a640_get_speed_bin(fuse); > > + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) > + val = a650_get_speed_bin(fuse); > + > if (val == UINT_MAX) { > DRM_DEV_ERROR(dev, > "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0ee8cb3e490c..c5f5d0bb3fdc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a650_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 1) + return 1; + else if (fuse == 2) + return 2; + else if (fuse == 3) + return 3; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + val = a650_get_speed_bin(fuse); + if (val == UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)