| Message ID | 20230227151318.1894938-1-m.grzeschik@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machines | expand |
On 2/27/23 16:13, Michael Grzeschik wrote: > An minimum udelay of 200 us seems to be necessary on some machines. After > the setup of the pll, which needs about 100 us to be locked there seem > to be additional 100 us to get the phy really functional. Without this > delay the usb runs not functional. With this additional short udelay > this issue was not reported again. > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > Hi Michael, Thank you for the updates, Fell free to add my: Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Best Regards, Fabrice > --- > v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice > - moved the delay to pll enable so it will only be triggered once > > drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c > index 5bb9647b078f12..dd469f57fba7eb 100644 > --- a/drivers/phy/st/phy-stm32-usbphyc.c > +++ b/drivers/phy/st/phy-stm32-usbphyc.c > @@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) > > stm32_usbphyc_set_bits(pll_reg, PLLEN); > > + /* Wait for maximum lock time */ > + usleep_range(200, 300); > + > return 0; > > reg_disable:
Hi Fabrice, On Tue, Feb 28, 2023 at 06:28:21PM +0100, Fabrice Gasnier wrote: >On 2/27/23 16:13, Michael Grzeschik wrote: >> An minimum udelay of 200 us seems to be necessary on some machines. After >> the setup of the pll, which needs about 100 us to be locked there seem >> to be additional 100 us to get the phy really functional. Without this >> delay the usb runs not functional. With this additional short udelay >> this issue was not reported again. >> >> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >> > >Hi Michael, > >Thank you for the updates, > >Fell free to add my: >Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Thanks! Trhough which tree will this be picked? Wil it be possible to add this to v6.3? Regards, Michael >> --- >> v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice >> - moved the delay to pll enable so it will only be triggered once >> >> drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c >> index 5bb9647b078f12..dd469f57fba7eb 100644 >> --- a/drivers/phy/st/phy-stm32-usbphyc.c >> +++ b/drivers/phy/st/phy-stm32-usbphyc.c >> @@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) >> >> stm32_usbphyc_set_bits(pll_reg, PLLEN); >> >> + /* Wait for maximum lock time */ >> + usleep_range(200, 300); >> + >> return 0; >> >> reg_disable: >
Gentle Ping! On Fri, Mar 10, 2023 at 11:44:38AM +0100, Michael Grzeschik wrote: >Hi Fabrice, > >On Tue, Feb 28, 2023 at 06:28:21PM +0100, Fabrice Gasnier wrote: >>On 2/27/23 16:13, Michael Grzeschik wrote: >>>An minimum udelay of 200 us seems to be necessary on some machines. After >>>the setup of the pll, which needs about 100 us to be locked there seem >>>to be additional 100 us to get the phy really functional. Without this >>>delay the usb runs not functional. With this additional short udelay >>>this issue was not reported again. >>> >>>Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >>> >> >>Hi Michael, >> >>Thank you for the updates, >> >>Fell free to add my: >>Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> > >Thanks! > >Through which tree will this be picked? >Will it be possible to add this to v6.3? > >Regards, >Michael > >>>--- >>>v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice >>> - moved the delay to pll enable so it will only be triggered once >>> >>> drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>>diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c >>>index 5bb9647b078f12..dd469f57fba7eb 100644 >>>--- a/drivers/phy/st/phy-stm32-usbphyc.c >>>+++ b/drivers/phy/st/phy-stm32-usbphyc.c >>>@@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) >>> >>> stm32_usbphyc_set_bits(pll_reg, PLLEN); >>> >>>+ /* Wait for maximum lock time */ >>>+ usleep_range(200, 300); >>>+ >>> return 0; >>> >>> reg_disable: >> > >-- >Pengutronix e.K. | | >Steuerwalder Str. 21 | http://www.pengutronix.de/ | >31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | >Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Cc'ing: Greg Kroah-Hartman <gregkh@linuxfoundation.org> On Mon, Mar 20, 2023 at 01:02:10PM +0100, Michael Grzeschik wrote: >Gentle Ping! > >On Fri, Mar 10, 2023 at 11:44:38AM +0100, Michael Grzeschik wrote: >>Hi Fabrice, >> >>On Tue, Feb 28, 2023 at 06:28:21PM +0100, Fabrice Gasnier wrote: >>>On 2/27/23 16:13, Michael Grzeschik wrote: >>>>An minimum udelay of 200 us seems to be necessary on some machines. After >>>>the setup of the pll, which needs about 100 us to be locked there seem >>>>to be additional 100 us to get the phy really functional. Without this >>>>delay the usb runs not functional. With this additional short udelay >>>>this issue was not reported again. >>>> >>>>Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> >>>> >>> >>>Hi Michael, >>> >>>Thank you for the updates, >>> >>>Fell free to add my: >>>Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> >> >>Thanks! >> >>Through which tree will this be picked? >>Will it be possible to add this to v6.3? Hi Greg! Since nobody seem to catch this, is it possible that you pick this? Regards, Michael >>>>--- >>>>v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice >>>> - moved the delay to pll enable so it will only be triggered once >>>> >>>>drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ >>>>1 file changed, 3 insertions(+) >>>> >>>>diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c >>>>index 5bb9647b078f12..dd469f57fba7eb 100644 >>>>--- a/drivers/phy/st/phy-stm32-usbphyc.c >>>>+++ b/drivers/phy/st/phy-stm32-usbphyc.c >>>>@@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) >>>> >>>> stm32_usbphyc_set_bits(pll_reg, PLLEN); >>>> >>>>+ /* Wait for maximum lock time */ >>>>+ usleep_range(200, 300); >>>>+ >>>> return 0; >>>> >>>>reg_disable: >>> >> >>-- >>Pengutronix e.K. | | >>Steuerwalder Str. 21 | http://www.pengutronix.de/ | >>31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | >>Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > > > >>_______________________________________________ >>linux-arm-kernel mailing list >>linux-arm-kernel@lists.infradead.org >>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > >-- >Pengutronix e.K. | | >Steuerwalder Str. 21 | http://www.pengutronix.de/ | >31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | >Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, Mar 31, 2023 at 02:06:27PM +0200, Michael Grzeschik wrote: > Cc'ing: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > > On Mon, Mar 20, 2023 at 01:02:10PM +0100, Michael Grzeschik wrote: > > Gentle Ping! > > > > On Fri, Mar 10, 2023 at 11:44:38AM +0100, Michael Grzeschik wrote: > > > Hi Fabrice, > > > > > > On Tue, Feb 28, 2023 at 06:28:21PM +0100, Fabrice Gasnier wrote: > > > > On 2/27/23 16:13, Michael Grzeschik wrote: > > > > > An minimum udelay of 200 us seems to be necessary on some machines. After > > > > > the setup of the pll, which needs about 100 us to be locked there seem > > > > > to be additional 100 us to get the phy really functional. Without this > > > > > delay the usb runs not functional. With this additional short udelay > > > > > this issue was not reported again. > > > > > > > > > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > > > > > > > > > > > > > Hi Michael, > > > > > > > > Thank you for the updates, > > > > > > > > Fell free to add my: > > > > Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> > > > > > > Thanks! > > > > > > Through which tree will this be picked? > > > Will it be possible to add this to v6.3? > > Hi Greg! > > Since nobody seem to catch this, is it possible that you pick this? What is "this"? The change to the following file: > > > > > --- > > > > > v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice > > > > > - moved the delay to pll enable so it will only be triggered once > > > > > > > > > > drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ > > > > > 1 file changed, 3 insertions(+) That one? I'm not anywhere on the maintainer path for it: $ ./scripts/get_maintainer.pl drivers/phy/st/phy-stm32-usbphyc.c Vinod Koul <vkoul@kernel.org> (supporter:GENERIC PHY FRAMEWORK,commit_signer:3/3=100%) Kishon Vijay Abraham I <kishon@kernel.org> (supporter:GENERIC PHY FRAMEWORK) Maxime Coquelin <mcoquelin.stm32@gmail.com> (maintainer:ARM/STM32 ARCHITECTURE) Alexandre Torgue <alexandre.torgue@foss.st.com> (maintainer:ARM/STM32 ARCHITECTURE) Philipp Zabel <p.zabel@pengutronix.de> (maintainer:RESET CONTROLLER FRAMEWORK) Liam Girdwood <lgirdwood@gmail.com> (supporter:VOLTAGE AND CURRENT REGULATOR FRAMEWORK) Mark Brown <broonie@kernel.org> (supporter:VOLTAGE AND CURRENT REGULATOR FRAMEWORK) Amelie Delaunay <amelie.delaunay@foss.st.com> (commit_signer:2/3=67%) Dan Carpenter <error27@gmail.com> (commit_signer:2/3=67%,authored:2/3=67%,added_lines:4/7=57%) Fabrice Gasnier <fabrice.gasnier@foss.st.com> (commit_signer:1/3=33%,authored:1/3=33%,added_lines:3/7=43%,removed_lines:1/1=100%) linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK) linux-stm32@st-md-mailman.stormreply.com (moderated list:ARM/STM32 ARCHITECTURE) linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) linux-kernel@vger.kernel.org (open list) What happened to the maintainers involved here? thanks, greg k-h
On 31-03-23, 15:19, Greg KH wrote: > On Fri, Mar 31, 2023 at 02:06:27PM +0200, Michael Grzeschik wrote: > > Cc'ing: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > > > > > On Mon, Mar 20, 2023 at 01:02:10PM +0100, Michael Grzeschik wrote: > > > Gentle Ping! > > > > > > On Fri, Mar 10, 2023 at 11:44:38AM +0100, Michael Grzeschik wrote: > > > > Hi Fabrice, > > > > > > > > On Tue, Feb 28, 2023 at 06:28:21PM +0100, Fabrice Gasnier wrote: > > > > > On 2/27/23 16:13, Michael Grzeschik wrote: > > > > > > An minimum udelay of 200 us seems to be necessary on some machines. After > > > > > > the setup of the pll, which needs about 100 us to be locked there seem > > > > > > to be additional 100 us to get the phy really functional. Without this > > > > > > delay the usb runs not functional. With this additional short udelay > > > > > > this issue was not reported again. > > > > > > > > > > > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > > > > > > > > > > > > > > > > Hi Michael, > > > > > > > > > > Thank you for the updates, > > > > > > > > > > Fell free to add my: > > > > > Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> > > > > > > > > Thanks! > > > > > > > > Through which tree will this be picked? > > > > Will it be possible to add this to v6.3? > > > > Hi Greg! > > > > Since nobody seem to catch this, is it possible that you pick this? > > What is "this"? The change to the following file: > > > > > > > --- > > > > > > v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice > > > > > > - moved the delay to pll enable so it will only be triggered once > > > > > > > > > > > > drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ > > > > > > 1 file changed, 3 insertions(+) > > That one? > > I'm not anywhere on the maintainer path for it: > > $ ./scripts/get_maintainer.pl drivers/phy/st/phy-stm32-usbphyc.c > Vinod Koul <vkoul@kernel.org> (supporter:GENERIC PHY FRAMEWORK,commit_signer:3/3=100%) > Kishon Vijay Abraham I <kishon@kernel.org> (supporter:GENERIC PHY FRAMEWORK) > Maxime Coquelin <mcoquelin.stm32@gmail.com> (maintainer:ARM/STM32 ARCHITECTURE) > Alexandre Torgue <alexandre.torgue@foss.st.com> (maintainer:ARM/STM32 ARCHITECTURE) > Philipp Zabel <p.zabel@pengutronix.de> (maintainer:RESET CONTROLLER FRAMEWORK) > Liam Girdwood <lgirdwood@gmail.com> (supporter:VOLTAGE AND CURRENT REGULATOR FRAMEWORK) > Mark Brown <broonie@kernel.org> (supporter:VOLTAGE AND CURRENT REGULATOR FRAMEWORK) > Amelie Delaunay <amelie.delaunay@foss.st.com> (commit_signer:2/3=67%) > Dan Carpenter <error27@gmail.com> (commit_signer:2/3=67%,authored:2/3=67%,added_lines:4/7=57%) > Fabrice Gasnier <fabrice.gasnier@foss.st.com> (commit_signer:1/3=33%,authored:1/3=33%,added_lines:3/7=43%,removed_lines:1/1=100%) > linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK) > linux-stm32@st-md-mailman.stormreply.com (moderated list:ARM/STM32 ARCHITECTURE) > linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) > linux-kernel@vger.kernel.org (open list) > > > What happened to the maintainers involved here? That would be me, sorry to have missed this one. I should be able to review and do the needful shortly
On 27-02-23, 16:13, Michael Grzeschik wrote: > An minimum udelay of 200 us seems to be necessary on some machines. After > the setup of the pll, which needs about 100 us to be locked there seem > to be additional 100 us to get the phy really functional. Without this > delay the usb runs not functional. With this additional short udelay > this issue was not reported again. Applied, thanks
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c index 5bb9647b078f12..dd469f57fba7eb 100644 --- a/drivers/phy/st/phy-stm32-usbphyc.c +++ b/drivers/phy/st/phy-stm32-usbphyc.c @@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) stm32_usbphyc_set_bits(pll_reg, PLLEN); + /* Wait for maximum lock time */ + usleep_range(200, 300); + return 0; reg_disable:
An minimum udelay of 200 us seems to be necessary on some machines. After the setup of the pll, which needs about 100 us to be locked there seem to be additional 100 us to get the phy really functional. Without this delay the usb runs not functional. With this additional short udelay this issue was not reported again. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice - moved the delay to pll enable so it will only be triggered once drivers/phy/st/phy-stm32-usbphyc.c | 3 +++ 1 file changed, 3 insertions(+)