| Message ID | 20230407093237.3296286-1-lionel.g.landwerlin@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: disable sampler indirect state in bindless heap | expand |
On 07/04/2023 12:32, Lionel Landwerlin wrote: > By default the indirect state sampler data (border colors) are stored > in the same heap as the SAMPLER_STATE structure. For userspace drivers > that can be 2 different heaps (dynamic state heap & bindless sampler > state heap). This means that border colors have to copied in 2 > different places so that the same SAMPLER_STATE structure find the > right data. > > This change is forcing the indirect state sampler data to only be in > the dynamic state pool (more convinient for userspace drivers, they > only have to have one copy of the border colors). This is reproducing > the behavior of the Windows drivers. > > BSpec: 46052 > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Cc: stable@vger.kernel.org > Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Screwed up the subject-prefix, but this is v4. Rebased due to another change touching the same register. -Lionel > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 492b3de6678d7..fd1f9cd35e9d7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1145,6 +1145,7 @@ > #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) > #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) > +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) > > #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) > #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6ea453ddd0116..b925ef47304b6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > add_render_compute_tuning_settings(i915, wal); > > + if (GRAPHICS_VER(i915) >= 11) { > + /* This is not a Wa (although referred to as > + * WaSetInidrectStateOverride in places), this allows > + * applications that reference sampler states through > + * the BindlessSamplerStateBaseAddress to have their > + * border color relative to DynamicStateBaseAddress > + * rather than BindlessSamplerStateBaseAddress. > + * > + * Otherwise SAMPLER_STATE border colors have to be > + * copied in multiple heaps (DynamicStateBaseAddress & > + * BindlessSamplerStateBaseAddress) > + * > + * BSpec: 46052 > + */ > + wa_mcr_masked_en(wal, > + GEN10_SAMPLER_MODE, > + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); > + } > + > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) > /* Wa_14017856879 */
On Fri, Apr 07, 2023 at 12:32:37PM +0300, Lionel Landwerlin wrote: > By default the indirect state sampler data (border colors) are stored > in the same heap as the SAMPLER_STATE structure. For userspace drivers > that can be 2 different heaps (dynamic state heap & bindless sampler > state heap). This means that border colors have to copied in 2 > different places so that the same SAMPLER_STATE structure find the > right data. > > This change is forcing the indirect state sampler data to only be in > the dynamic state pool (more convinient for userspace drivers, they > only have to have one copy of the border colors). This is reproducing > the behavior of the Windows drivers. > > BSpec: 46052 > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Cc: stable@vger.kernel.org > Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Applied to drm-intel-gt-next. Thanks for the patch and review. Matt > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 492b3de6678d7..fd1f9cd35e9d7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1145,6 +1145,7 @@ > #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) > #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) > +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) > > #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) > #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6ea453ddd0116..b925ef47304b6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > add_render_compute_tuning_settings(i915, wal); > > + if (GRAPHICS_VER(i915) >= 11) { > + /* This is not a Wa (although referred to as > + * WaSetInidrectStateOverride in places), this allows > + * applications that reference sampler states through > + * the BindlessSamplerStateBaseAddress to have their > + * border color relative to DynamicStateBaseAddress > + * rather than BindlessSamplerStateBaseAddress. > + * > + * Otherwise SAMPLER_STATE border colors have to be > + * copied in multiple heaps (DynamicStateBaseAddress & > + * BindlessSamplerStateBaseAddress) > + * > + * BSpec: 46052 > + */ > + wa_mcr_masked_en(wal, > + GEN10_SAMPLER_MODE, > + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); > + } > + > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) > /* Wa_14017856879 */ > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 492b3de6678d7..fd1f9cd35e9d7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1145,6 +1145,7 @@ #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6ea453ddd0116..b925ef47304b6 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li add_render_compute_tuning_settings(i915, wal); + if (GRAPHICS_VER(i915) >= 11) { + /* This is not a Wa (although referred to as + * WaSetInidrectStateOverride in places), this allows + * applications that reference sampler states through + * the BindlessSamplerStateBaseAddress to have their + * border color relative to DynamicStateBaseAddress + * rather than BindlessSamplerStateBaseAddress. + * + * Otherwise SAMPLER_STATE border colors have to be + * copied in multiple heaps (DynamicStateBaseAddress & + * BindlessSamplerStateBaseAddress) + * + * BSpec: 46052 + */ + wa_mcr_masked_en(wal, + GEN10_SAMPLER_MODE, + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); + } + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) /* Wa_14017856879 */