| Message ID | 20230407105029.2274111-7-abel.vesa@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add dedicated Qcom ICE driver | expand |
On Fri, Apr 07, 2023 at 01:50:29PM +0300, Abel Vesa wrote: > Add support for UFS ICE by adding the qcom,ice property and the > ICE dedicated devicetree node. While at it, add the reg-name property > to the UFS HC node to be in line with older platforms. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > > The v5 is here: > https://lore.kernel.org/all/20230403200530.2103099-7-abel.vesa@linaro.org/ > > Changes since v5: > * Dropped the reg-names property from UFS node as it was not needed and > makes the bindings check fail You forgot to drop the related sentence from the commit message. Regards, Bjorn > > Changes since v4: > * none > > Changes since v3: > * none > > arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index d252658c73dd..2b3a721292b6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1932,9 +1932,18 @@ ufs_mem_hc: ufs@1d84000 { > <0 0>, > <0 0>, > <0 0>; > + qcom,ice = <&ice>; > + > status = "disabled"; > }; > > + ice: crypto@1d88000 { > + compatible = "qcom,sm8550-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0 0x01d88000 0 0x8000>; > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0 0x01f40000 0 0x20000>; > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d252658c73dd..2b3a721292b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1932,9 +1932,18 @@ ufs_mem_hc: ufs@1d84000 { <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8550-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>;
Add support for UFS ICE by adding the qcom,ice property and the ICE dedicated devicetree node. While at it, add the reg-name property to the UFS HC node to be in line with older platforms. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- The v5 is here: https://lore.kernel.org/all/20230403200530.2103099-7-abel.vesa@linaro.org/ Changes since v5: * Dropped the reg-names property from UFS node as it was not needed and makes the bindings check fail Changes since v4: * none Changes since v3: * none arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)