diff mbox series

[v1,1/2] ARM: dts: aspeed: greatlakes: Add gpio names

Message ID 20230329083235.24123-2-Delphine_CC_Chiu@Wiwynn.com (mailing list archive)
State New, archived
Headers show
Series dts: aspeed: greatlakes: Update Greatlakes devicetree | expand

Commit Message

Delphine CC Chiu March 29, 2023, 8:32 a.m. UTC
From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>

Add GPIO names for SOC lines.

Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
 .../dts/aspeed-bmc-facebook-greatlakes.dts    | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

Comments

Krzysztof Kozlowski March 29, 2023, 8:36 a.m. UTC | #1
On 29/03/2023 10:32, Delphine CC Chiu wrote:
> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> 
> Add GPIO names for SOC lines.
> 
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
>  .../dts/aspeed-bmc-facebook-greatlakes.dts    | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> index 8c05bd56ce1e..59819115c39d 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> @@ -238,4 +238,53 @@
>  &gpio0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> +	status = "okay";

Was it disabled before?

> +	gpio-line-names =
> +	/*A0-A7*/ "","","","","","","","",
> +	/*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> +		  "power-bmc-slot1","power-bmc-slot2",
> +		  "power-bmc-slot3","power-bmc-slot4","","",
> +	/*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> +		  "reset-cause-nic-secondary","","","",
> +	/*D0-D7*/ "","","","","","","","",
> +	/*E0-E7*/ "","","","","","","","",
> +	/*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> +		  "slot3-bmc-reset-button","slot4-bmc-reset-button",
> +		  "","","","presence-emmc",
> +	/*G0-G7*/ "","","","","","","","",
> +	/*H0-H7*/ "","","","",
> +		  "presence-mb-slot1","presence-mb-slot2",
> +		  "presence-mb-slot3","presence-mb-slot4",
> +	/*I0-I7*/ "","","","","","","bb-bmc-button","",
> +	/*J0-J7*/ "","","","","","","","",
> +	/*K0-K7*/ "","","","","","","","",
> +	/*L0-L7*/ "","","","","","","","",
> +	/*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
> +	/*N0-N7*/ "","","","","bmc-ready","","","",
> +	/*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> +	/*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> +		  "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> +		  "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> +	/*Q0-Q7*/ "","","","","","","","",
> +	/*R0-R7*/ "","","","","","","","",
> +	/*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> +	/*T0-T7*/ "","","","","","","","",
> +	/*U0-U7*/ "","","","","","","","GND",
> +	/*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> +		  "bmc-slot3-ac-button","bmc-slot4-ac-button",
> +		  "","","","",
> +	/*W0-W7*/ "","","","","","","","",
> +	/*X0-X7*/ "","","","","","","","",
> +	/*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> +	/*Z0-Z7*/ "","","","","","","","";
> +};
> +
> +&gpio1 {
> +	status = "okay";

Same question...
Best regards,
Krzysztof
Delphine CC Chiu April 10, 2023, 7:11 a.m. UTC | #2
Thank you for reviewing.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, March 29, 2023 4:37 PM
> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
> Jeffery <andrew@aj.id.au>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
> 
>   Security Reminder: Please be aware that this email is sent by an external
> sender.
> 
> On 29/03/2023 10:32, Delphine CC Chiu wrote:
> > From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >
> > Add GPIO names for SOC lines.
> >
> > Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> > ---
> >  .../dts/aspeed-bmc-facebook-greatlakes.dts    | 49
> +++++++++++++++++++
> >  1 file changed, 49 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > index 8c05bd56ce1e..59819115c39d 100644
> > --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > @@ -238,4 +238,53 @@
> >  &gpio0 {
> >       pinctrl-names = "default";
> >       pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> > +     status = "okay";
> 
> Was it disabled before?
> 
Yes, we have to enable gpio status for meeting aspeed-g6 device tree setting, and set net names for pulling gpio pin from application layer.
> > +     gpio-line-names =
> > +     /*A0-A7*/ "","","","","","","","",
> > +     /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> > +               "power-bmc-slot1","power-bmc-slot2",
> > +               "power-bmc-slot3","power-bmc-slot4","","",
> > +     /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> > +               "reset-cause-nic-secondary","","","",
> > +     /*D0-D7*/ "","","","","","","","",
> > +     /*E0-E7*/ "","","","","","","","",
> > +     /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> > +               "slot3-bmc-reset-button","slot4-bmc-reset-button",
> > +               "","","","presence-emmc",
> > +     /*G0-G7*/ "","","","","","","","",
> > +     /*H0-H7*/ "","","","",
> > +               "presence-mb-slot1","presence-mb-slot2",
> > +               "presence-mb-slot3","presence-mb-slot4",
> > +     /*I0-I7*/ "","","","","","","bb-bmc-button","",
> > +     /*J0-J7*/ "","","","","","","","",
> > +     /*K0-K7*/ "","","","","","","","",
> > +     /*L0-L7*/ "","","","","","","","",
> > +     /*M0-M7*/
> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
> > +     /*N0-N7*/ "","","","","bmc-ready","","","",
> > +     /*O0-O7*/
> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> > +     /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> > +               "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> > +               "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> > +     /*Q0-Q7*/ "","","","","","","","",
> > +     /*R0-R7*/ "","","","","","","","",
> > +     /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> > +     /*T0-T7*/ "","","","","","","","",
> > +     /*U0-U7*/ "","","","","","","","GND",
> > +     /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> > +               "bmc-slot3-ac-button","bmc-slot4-ac-button",
> > +               "","","","",
> > +     /*W0-W7*/ "","","","","","","","",
> > +     /*X0-X7*/ "","","","","","","","",
> > +     /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> > +     /*Z0-Z7*/ "","","","","","","",""; };
> > +
> > +&gpio1 {
> > +     status = "okay";
> 
> Same question...
Yes, the answer is same as above.
> Best regards,
> Krzysztof
Krzysztof Kozlowski April 10, 2023, 3:21 p.m. UTC | #3
On 10/04/2023 09:11, Delphine_CC_Chiu/WYHQ/Wiwynn wrote:
> Thank you for reviewing.
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Wednesday, March 29, 2023 4:37 PM
>> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
>> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
>> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
>> Jeffery <andrew@aj.id.au>
>> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
>>
>>   Security Reminder: Please be aware that this email is sent by an external
>> sender.
>>
>> On 29/03/2023 10:32, Delphine CC Chiu wrote:
>>> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
>>>
>>> Add GPIO names for SOC lines.
>>>
>>> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
>>> ---
>>>  .../dts/aspeed-bmc-facebook-greatlakes.dts    | 49
>> +++++++++++++++++++
>>>  1 file changed, 49 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> index 8c05bd56ce1e..59819115c39d 100644
>>> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> @@ -238,4 +238,53 @@
>>>  &gpio0 {
>>>       pinctrl-names = "default";
>>>       pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
>>> +     status = "okay";
>>
>> Was it disabled before?
>>
> Yes, 

Really? Can you provide any proof for this?

> we have to enable gpio status for meeting aspeed-g6 device tree setting, and set net names for pulling gpio pin from application layer.

What is "enable gpio status"? What does it mean to "meet aspeeg-g6
devicetree setting"?
What names have anything to do with my question?

Sorry, I cannot parse it at all.

>>> +     gpio-line-names =
>>> +     /*A0-A7*/ "","","","","","","","",
>>> +     /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
>>> +               "power-bmc-slot1","power-bmc-slot2",
>>> +               "power-bmc-slot3","power-bmc-slot4","","",
>>> +     /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
>>> +               "reset-cause-nic-secondary","","","",
>>> +     /*D0-D7*/ "","","","","","","","",
>>> +     /*E0-E7*/ "","","","","","","","",
>>> +     /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
>>> +               "slot3-bmc-reset-button","slot4-bmc-reset-button",
>>> +               "","","","presence-emmc",
>>> +     /*G0-G7*/ "","","","","","","","",
>>> +     /*H0-H7*/ "","","","",
>>> +               "presence-mb-slot1","presence-mb-slot2",
>>> +               "presence-mb-slot3","presence-mb-slot4",
>>> +     /*I0-I7*/ "","","","","","","bb-bmc-button","",
>>> +     /*J0-J7*/ "","","","","","","","",
>>> +     /*K0-K7*/ "","","","","","","","",
>>> +     /*L0-L7*/ "","","","","","","","",
>>> +     /*M0-M7*/
>> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
>>> +     /*N0-N7*/ "","","","","bmc-ready","","","",
>>> +     /*O0-O7*/
>> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
>>> +     /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
>>> +               "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
>>> +               "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
>>> +     /*Q0-Q7*/ "","","","","","","","",
>>> +     /*R0-R7*/ "","","","","","","","",
>>> +     /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
>>> +     /*T0-T7*/ "","","","","","","","",
>>> +     /*U0-U7*/ "","","","","","","","GND",
>>> +     /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
>>> +               "bmc-slot3-ac-button","bmc-slot4-ac-button",
>>> +               "","","","",
>>> +     /*W0-W7*/ "","","","","","","","",
>>> +     /*X0-X7*/ "","","","","","","","",
>>> +     /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
>>> +     /*Z0-Z7*/ "","","","","","","",""; };
>>> +
>>> +&gpio1 {
>>> +     status = "okay";
>>
>> Same question...
> Yes, the answer is same as above.

So the same incorrect?


Best regards,
Krzysztof
Delphine CC Chiu April 24, 2023, 9:50 a.m. UTC | #4
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Monday, April 10, 2023 11:21 PM
> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
> Jeffery <andrew@aj.id.au>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
> 
>   Security Reminder: Please be aware that this email is sent by an external
> sender.
> 
> On 10/04/2023 09:11, Delphine_CC_Chiu/WYHQ/Wiwynn wrote:
> > Thank you for reviewing.
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> Sent: Wednesday, March 29, 2023 4:37 PM
> >> To: Delphine_CC_Chiu/WYHQ/Wiwynn
> <Delphine_CC_Chiu@wiwynn.com>;
> >> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof
> >> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley
> >> <joel@jms.id.au>; Andrew Jeffery <andrew@aj.id.au>
> >> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio
> >> names
> >>
> >>   Security Reminder: Please be aware that this email is sent by an
> >> external sender.
> >>
> >> On 29/03/2023 10:32, Delphine CC Chiu wrote:
> >>> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >>>
> >>> Add GPIO names for SOC lines.
> >>>
> >>> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >>> ---
> >>>  .../dts/aspeed-bmc-facebook-greatlakes.dts    | 49
> >> +++++++++++++++++++
> >>>  1 file changed, 49 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> index 8c05bd56ce1e..59819115c39d 100644
> >>> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> @@ -238,4 +238,53 @@
> >>>  &gpio0 {
> >>>       pinctrl-names = "default";
> >>>       pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> >>> +     status = "okay";
> >>
> >> Was it disabled before?
> >>
> > Yes,
> 
> Really? Can you provide any proof for this?
Correct the answer after verifying - when gpio0 status property is not defined, it leads to device default enabled.
> 
> > we have to enable gpio status for meeting aspeed-g6 device tree setting,
> and set net names for pulling gpio pin from application layer.
> 
> What is "enable gpio status"? What does it mean to "meet aspeeg-g6
> devicetree setting"?
> What names have anything to do with my question?
> 
> Sorry, I cannot parse it at all.
To describe more precisely, I surveyed the identification of of_device_is_available() in drivers/of/base.c.
It returns true if the status property is absent or set to "okay" or "ok", and false otherwise.
Because gpio0 status property hasn’t defined in aspeed-g6.dtsi, I set to "okay" to prevent that if it was disabled from other assignment.
> 
> >>> +     gpio-line-names =
> >>> +     /*A0-A7*/ "","","","","","","","",
> >>> +     /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> >>> +               "power-bmc-slot1","power-bmc-slot2",
> >>> +               "power-bmc-slot3","power-bmc-slot4","","",
> >>> +     /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> >>> +               "reset-cause-nic-secondary","","","",
> >>> +     /*D0-D7*/ "","","","","","","","",
> >>> +     /*E0-E7*/ "","","","","","","","",
> >>> +     /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> >>> +               "slot3-bmc-reset-button","slot4-bmc-reset-button",
> >>> +               "","","","presence-emmc",
> >>> +     /*G0-G7*/ "","","","","","","","",
> >>> +     /*H0-H7*/ "","","","",
> >>> +               "presence-mb-slot1","presence-mb-slot2",
> >>> +               "presence-mb-slot3","presence-mb-slot4",
> >>> +     /*I0-I7*/ "","","","","","","bb-bmc-button","",
> >>> +     /*J0-J7*/ "","","","","","","","",
> >>> +     /*K0-K7*/ "","","","","","","","",
> >>> +     /*L0-L7*/ "","","","","","","","",
> >>> +     /*M0-M7*/
> >> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub
> >> ","","",
> >>> +     /*N0-N7*/ "","","","","bmc-ready","","","",
> >>> +     /*O0-O7*/
> >> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> >>> +     /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> >>> +               "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> >>> +
> "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> >>> +     /*Q0-Q7*/ "","","","","","","","",
> >>> +     /*R0-R7*/ "","","","","","","","",
> >>> +     /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> >>> +     /*T0-T7*/ "","","","","","","","",
> >>> +     /*U0-U7*/ "","","","","","","","GND",
> >>> +     /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> >>> +               "bmc-slot3-ac-button","bmc-slot4-ac-button",
> >>> +               "","","","",
> >>> +     /*W0-W7*/ "","","","","","","","",
> >>> +     /*X0-X7*/ "","","","","","","","",
> >>> +     /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> >>> +     /*Z0-Z7*/ "","","","","","","",""; };
> >>> +
> >>> +&gpio1 {
> >>> +     status = "okay";
> >>
> >> Same question...
> > Yes, the answer is same as above.
> 
> So the same incorrect?
The status property of gpio1 was also default enabled.
For same reason as gpio0, I set to "okay" from this patch.
> 
> 
> Best regards,
> Krzysztof
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
index 8c05bd56ce1e..59819115c39d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
@@ -238,4 +238,53 @@ 
 &gpio0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
+	status = "okay";
+	gpio-line-names =
+	/*A0-A7*/ "","","","","","","","",
+	/*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
+		  "power-bmc-slot1","power-bmc-slot2",
+		  "power-bmc-slot3","power-bmc-slot4","","",
+	/*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
+		  "reset-cause-nic-secondary","","","",
+	/*D0-D7*/ "","","","","","","","",
+	/*E0-E7*/ "","","","","","","","",
+	/*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
+		  "slot3-bmc-reset-button","slot4-bmc-reset-button",
+		  "","","","presence-emmc",
+	/*G0-G7*/ "","","","","","","","",
+	/*H0-H7*/ "","","","",
+		  "presence-mb-slot1","presence-mb-slot2",
+		  "presence-mb-slot3","presence-mb-slot4",
+	/*I0-I7*/ "","","","","","","bb-bmc-button","",
+	/*J0-J7*/ "","","","","","","","",
+	/*K0-K7*/ "","","","","","","","",
+	/*L0-L7*/ "","","","","","","","",
+	/*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
+	/*N0-N7*/ "","","","","bmc-ready","","","",
+	/*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
+	/*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
+		  "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
+		  "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
+	/*Q0-Q7*/ "","","","","","","","",
+	/*R0-R7*/ "","","","","","","","",
+	/*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
+	/*T0-T7*/ "","","","","","","","",
+	/*U0-U7*/ "","","","","","","","GND",
+	/*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
+		  "bmc-slot3-ac-button","bmc-slot4-ac-button",
+		  "","","","",
+	/*W0-W7*/ "","","","","","","","",
+	/*X0-X7*/ "","","","","","","","",
+	/*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
+	/*Z0-Z7*/ "","","","","","","","";
+};
+
+&gpio1 {
+	status = "okay";
+	gpio-line-names =
+	/*18A0-18A7*/ "","","","","","","","",
+	/*18B0-18B7*/ "","","","","","","","",
+	/*18C0-18C7*/ "","","","","","","","",
+	/*18D0-18D7*/ "","","","","","","","",
+	/*18E0-18E3*/ "","","","","","","","";
 };