diff mbox series

[v5,10/12] arm64: dts: mediatek: add OPP support for mt8365 SoC

Message ID 20230203-evk-board-support-v5-10-1883c1b405ad@baylibre.com (mailing list archive)
State New, archived
Headers show
Series Improve the MT8365 SoC and EVK board support | expand

Commit Message

Alexandre Mergnat April 7, 2023, 12:59 p.m. UTC 
In order to have cpufreq support, this patch adds generic Operating
Performance Points support.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

Comments

Alexandre Mergnat April 7, 2023, 1:14 p.m. UTC | #1 
+ To: Catalin Marinas <catalin.marinas@arm.com>
+ To: Will Deacon <will@kernel.org>

Sorry for the noise.

Regards,
Alexandre

Le ven. 7 avr. 2023 à 14:59, Alexandre Mergnat <amergnat@baylibre.com> a écrit :
>
> In order to have cpufreq support, this patch adds generic Operating
> Performance Points support.
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index bb45aab2e6a9..cfe0c67ad61f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -20,6 +20,91 @@ cpus {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>
> +       cluster0_opp: opp-table-0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-850000000 {
> +                       opp-hz = /bits/ 64 <850000000>;
> +                       opp-microvolt = <650000>;
> +               };
> +
> +               opp-918000000 {
> +                       opp-hz = /bits/ 64 <918000000>;
> +                       opp-microvolt = <668750>;
> +               };
> +
> +               opp-987000000 {
> +                       opp-hz = /bits/ 64 <987000000>;
> +                       opp-microvolt = <687500>;
> +               };
> +
> +               opp-1056000000 {
> +                       opp-hz = /bits/ 64 <1056000000>;
> +                       opp-microvolt = <706250>;
> +               };
> +
> +               opp-1125000000 {
> +                       opp-hz = /bits/ 64 <1125000000>;
> +                       opp-microvolt = <725000>;
> +               };
> +
> +               opp-1216000000 {
> +                       opp-hz = /bits/ 64 <1216000000>;
> +                       opp-microvolt = <750000>;
> +               };
> +
> +               opp-1308000000 {
> +                       opp-hz = /bits/ 64 <1308000000>;
> +                       opp-microvolt = <775000>;
> +               };
> +
> +               opp-1400000000 {
> +                       opp-hz = /bits/ 64 <1400000000>;
> +                       opp-microvolt = <800000>;
> +               };
> +
> +               opp-1466000000 {
> +                       opp-hz = /bits/ 64 <1466000000>;
> +                       opp-microvolt = <825000>;
> +               };
> +
> +               opp-1533000000 {
> +                       opp-hz = /bits/ 64 <1533000000>;
> +                       opp-microvolt = <850000>;
> +               };
> +
> +               opp-1633000000 {
> +                       opp-hz = /bits/ 64 <1633000000>;
> +                       opp-microvolt = <887500>;
> +               };
> +
> +               opp-1700000000 {
> +                       opp-hz = /bits/ 64 <1700000000>;
> +                       opp-microvolt = <912500>;
> +               };
> +
> +               opp-1767000000 {
> +                       opp-hz = /bits/ 64 <1767000000>;
> +                       opp-microvolt = <937500>;
> +               };
> +
> +               opp-1834000000 {
> +                       opp-hz = /bits/ 64 <1834000000>;
> +                       opp-microvolt = <962500>;
> +               };
> +
> +               opp-1917000000 {
> +                       opp-hz = /bits/ 64 <1917000000>;
> +                       opp-microvolt = <993750>;
> +               };
> +
> +               opp-2001000000 {
> +                       opp-hz = /bits/ 64 <2001000000>;
> +                       opp-microvolt = <1025000>;
> +               };
> +       };
> +
>                 cpu-map {
>                         cluster0 {
>                                 core0 {
> @@ -50,6 +135,10 @@ cpu0: cpu@0 {
>                         d-cache-line-size = <64>;
>                         d-cache-sets = <256>;
>                         next-level-cache = <&l2>;
> +                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
> +                       clock-names = "cpu", "intermediate";
> +                       operating-points-v2 = <&cluster0_opp>;
>                 };
>
>                 cpu1: cpu@1 {
> @@ -65,6 +154,10 @@ cpu1: cpu@1 {
>                         d-cache-line-size = <64>;
>                         d-cache-sets = <256>;
>                         next-level-cache = <&l2>;
> +                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
> +                       clock-names = "cpu", "intermediate", "armpll";
> +                       operating-points-v2 = <&cluster0_opp>;
>                 };
>
>                 cpu2: cpu@2 {
> @@ -80,6 +173,10 @@ cpu2: cpu@2 {
>                         d-cache-line-size = <64>;
>                         d-cache-sets = <256>;
>                         next-level-cache = <&l2>;
> +                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
> +                       clock-names = "cpu", "intermediate", "armpll";
> +                       operating-points-v2 = <&cluster0_opp>;
>                 };
>
>                 cpu3: cpu@3 {
> @@ -95,6 +192,10 @@ cpu3: cpu@3 {
>                         d-cache-line-size = <64>;
>                         d-cache-sets = <256>;
>                         next-level-cache = <&l2>;
> +                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
> +                       clock-names = "cpu", "intermediate", "armpll";
> +                       operating-points-v2 = <&cluster0_opp>;
>                 };
>
>                 l2: l2-cache {
>
> --
> 2.25.1
>
AngeloGioacchino Del Regno April 11, 2023, 8:24 a.m. UTC | #2 
Il 07/04/23 14:59, Alexandre Mergnat ha scritto:
> In order to have cpufreq support, this patch adds generic Operating
> Performance Points support.
> 
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index bb45aab2e6a9..cfe0c67ad61f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -20,6 +20,91 @@  cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			opp-microvolt = <650000>;
+		};
+
+		opp-918000000 {
+			opp-hz = /bits/ 64 <918000000>;
+			opp-microvolt = <668750>;
+		};
+
+		opp-987000000 {
+			opp-hz = /bits/ 64 <987000000>;
+			opp-microvolt = <687500>;
+		};
+
+		opp-1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-microvolt = <706250>;
+		};
+
+		opp-1125000000 {
+			opp-hz = /bits/ 64 <1125000000>;
+			opp-microvolt = <725000>;
+		};
+
+		opp-1216000000 {
+			opp-hz = /bits/ 64 <1216000000>;
+			opp-microvolt = <750000>;
+		};
+
+		opp-1308000000 {
+			opp-hz = /bits/ 64 <1308000000>;
+			opp-microvolt = <775000>;
+		};
+
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <800000>;
+		};
+
+		opp-1466000000 {
+			opp-hz = /bits/ 64 <1466000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-1533000000 {
+			opp-hz = /bits/ 64 <1533000000>;
+			opp-microvolt = <850000>;
+		};
+
+		opp-1633000000 {
+			opp-hz = /bits/ 64 <1633000000>;
+			opp-microvolt = <887500>;
+		};
+
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <912500>;
+		};
+
+		opp-1767000000 {
+			opp-hz = /bits/ 64 <1767000000>;
+			opp-microvolt = <937500>;
+		};
+
+		opp-1834000000 {
+			opp-hz = /bits/ 64 <1834000000>;
+			opp-microvolt = <962500>;
+		};
+
+		opp-1917000000 {
+			opp-hz = /bits/ 64 <1917000000>;
+			opp-microvolt = <993750>;
+		};
+
+		opp-2001000000 {
+			opp-hz = /bits/ 64 <2001000000>;
+			opp-microvolt = <1025000>;
+		};
+	};
+
 		cpu-map {
 			cluster0 {
 				core0 {
@@ -50,6 +135,10 @@  cpu0: cpu@0 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2>;
+			clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@1 {
@@ -65,6 +154,10 @@  cpu1: cpu@1 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2>;
+			clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu@2 {
@@ -80,6 +173,10 @@  cpu2: cpu@2 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2>;
+			clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu3: cpu@3 {
@@ -95,6 +192,10 @@  cpu3: cpu@3 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2>;
+			clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		l2: l2-cache {