| Message ID | 20230411083257.16155-4-mason.huo@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add JH7110 cpufreq support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
Hey Mason, On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote: > Add the operating-points-v2 to support cpu scaling > on StarFive JH7110 SoC. (btw, there's no need to wrap commit messages at 52 columns, you have 72 to work with) > It supports up to 4 cpu frequency loads. > > Signed-off-by: Mason Huo <mason.huo@starfivetech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index df582bddae4b..ae446b268e78 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -228,3 +228,28 @@ &uart0 { > pinctrl-0 = <&uart0_pins>; > status = "okay"; > }; > + > +&U74_1 { > + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; > + clock-names = "cpu"; > + cpu-supply = <®_dcdc2>; > +}; > + > +&U74_2 { > + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; > + clock-names = "cpu"; > + cpu-supply = <®_dcdc2>; > +}; > + > +&U74_3 { > + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; > + clock-names = "cpu"; > + cpu-supply = <®_dcdc2>; > +}; > + > +&U74_4 { > + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ^^ There's a double space in each of these. > + clock-names = "cpu"; > + cpu-supply = <®_dcdc2>; > +}; How come these two clock properties are being added in <board>.dtsi? Should they not be in <soc>.dtsi? Thanks, Conor.
On 2023/4/11 17:06, Conor Dooley wrote: > Hey Mason, > > On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote: >> Add the operating-points-v2 to support cpu scaling >> on StarFive JH7110 SoC. > > (btw, there's no need to wrap commit messages at 52 columns, you have > 72 to work with) > Hi Conor, Thanks for your review. Will place it in the same line. >> It supports up to 4 cpu frequency loads. >> >> Signed-off-by: Mason Huo <mason.huo@starfivetech.com> >> --- >> .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++ >> 2 files changed, 50 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index df582bddae4b..ae446b268e78 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -228,3 +228,28 @@ &uart0 { >> pinctrl-0 = <&uart0_pins>; >> status = "okay"; >> }; >> + >> +&U74_1 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_2 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_3 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_4 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; > ^^ > There's a double space in each of these. > >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; > > How come these two clock properties are being added in <board>.dtsi? > Should they not be in <soc>.dtsi? >> Thanks, > Conor. Yes, will move them to <soc>.dtsi Thanks Mason
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index df582bddae4b..ae446b268e78 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -228,3 +228,28 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_2 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_3 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + +&U74_4 { + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + cpu-supply = <®_dcdc2>; +}; + diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..c867f968d054 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,7 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +80,7 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +107,7 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +134,7 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +168,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin";
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++ 2 files changed, 50 insertions(+)