| Message ID | 20230419061710.290068-2-j-choudhary@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add peripherals for J784S4 | expand |
On 19/04/2023 08:17, Jayesh Choudhary wrote: > From: Siddharth Vadapalli <s-vadapalli@ti.com> > > The system controller node manages the CTRL_MMR0 region. > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > [j-choudhary@ti.com: Minor cleanup to fix dtc warnings] > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index e9169eb358c1..5fb7edf4f5a0 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -5,6 +5,9 @@ > * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include <dt-bindings/mux/mux.h> > +#include <dt-bindings/mux/ti-serdes.h> > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -26,6 +29,25 @@ l3cache-sram@200000 { > }; > }; > > + scm_conf: syscon@100000 { > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; > + reg = <0x00 0x00100000 0x00 0x1c000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x00100000 0x1c000>; > + > + serdes_ln_ctrl: mux-controller-4080 { Does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). Best regards, Krzysztof
Hi Krzysztof, On 19/04/23 13:19, Krzysztof Kozlowski wrote: > On 19/04/2023 08:17, Jayesh Choudhary wrote: >> From: Siddharth Vadapalli <s-vadapalli@ti.com> >> >> The system controller node manages the CTRL_MMR0 region. >> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> [j-choudhary@ti.com: Minor cleanup to fix dtc warnings] >> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> index e9169eb358c1..5fb7edf4f5a0 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> @@ -5,6 +5,9 @@ >> * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ >> */ >> >> +#include <dt-bindings/mux/mux.h> >> +#include <dt-bindings/mux/ti-serdes.h> >> + >> &cbass_main { >> msmc_ram: sram@70000000 { >> compatible = "mmio-sram"; >> @@ -26,6 +29,25 @@ l3cache-sram@200000 { >> }; >> }; >> >> + scm_conf: syscon@100000 { >> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; >> + reg = <0x00 0x00100000 0x00 0x1c000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x00 0x00 0x00100000 0x1c000>; >> + >> + serdes_ln_ctrl: mux-controller-4080 { > > Does not look like you tested the DTS against bindings. Please run `make > dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst > for instructions). > Ohkay. The base seems to be from k3-j7200-main.dtsi which has the node name as mux-controller@4080 without reg property. After comments in v2, I used '-' instead of adding reg property to this node. Will change the node name again and add the reg property to fix the warning that I see now with dtbs_check. Thanks!!
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..5fb7edf4f5a0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/mux/mux.h> +#include <dt-bindings/mux/ti-serdes.h> + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +29,25 @@ l3cache-sram@200000 { }; }; + scm_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller-4080 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>;