| Message ID | 20230316202549.1764024-5-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | More MTL WA and powerwell patches | expand |
On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote: >From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > >If BIOS enables/disables C6, i915 should do the same. Also, retain >this value across driver reloads. This is needed only for MTL as >of now due to an existing bug in OA which needs C6 disabled for >it to function. BIOS behavior is also different across platforms >in terms of how C6 is enabled. > >v2: Review comments (Umesh) >v3: Cache the C6 enable value for all MTL. The OA WA is needed only >for A/B step, but we don't need to check for that here. >v4: Rename to mtl_check_bios_c6_setup() > >Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> This one's already pushed with the MTL OA series. Regards, Umesh
On Thu, Apr 20, 2023 at 01:05:27PM -0700, Umesh Nerlige Ramappa wrote: > On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote: > > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > > > If BIOS enables/disables C6, i915 should do the same. Also, retain > > this value across driver reloads. This is needed only for MTL as > > of now due to an existing bug in OA which needs C6 disabled for > > it to function. BIOS behavior is also different across platforms > > in terms of how C6 is enabled. > > > > v2: Review comments (Umesh) > > v3: Cache the C6 enable value for all MTL. The OA WA is needed only > > for A/B step, but we don't need to check for that here. > > v4: Rename to mtl_check_bios_c6_setup() > > > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > This one's already pushed with the MTL OA series. Thank you for the update. Skipped this patch in the latest rev at [1]. [1] https://patchwork.freedesktop.org/series/115292/#rev3 - Radhakrishna Sripada > > Regards, > Umesh
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index f4150f61f39c..517d14e29aac 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -420,6 +420,15 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; } +static bool mtl_check_bios_c6_setup(struct intel_rc6 *rc6) +{ + struct intel_uncore *uncore = rc6_to_uncore(rc6); + + rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE); + + return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK; +} + static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) { struct intel_uncore *uncore = rc6_to_uncore(rc6); @@ -503,6 +512,13 @@ static bool rc6_supported(struct intel_rc6 *rc6) return false; } + if (IS_METEORLAKE(gt->i915) && + !mtl_check_bios_c6_setup(rc6)) { + drm_notice(&i915->drm, + "C6 disabled by BIOS\n"); + return false; + } + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) && gt->type == GT_MEDIA) { drm_notice(&i915->drm, @@ -707,9 +723,14 @@ void intel_rc6_disable(struct intel_rc6 *rc6) void intel_rc6_fini(struct intel_rc6 *rc6) { struct drm_i915_gem_object *pctx; + struct intel_uncore *uncore = rc6_to_uncore(rc6); intel_rc6_disable(rc6); + /* We want the BIOS C6 state preserved across loads for MTL */ + if (IS_METEORLAKE(rc6_to_i915(rc6))) + set(uncore, GEN6_RC_STATE, rc6->bios_rc_state); + pctx = fetch_and_zero(&rc6->pctx); if (pctx) i915_gem_object_put(pctx); diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h index fa23c4dce00b..57bb437bcbbd 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h @@ -29,6 +29,7 @@ struct intel_rc6 { u64 cur_residency[INTEL_RC6_RES_MAX]; u32 ctl_enable; + u32 bios_rc_state; struct drm_i915_gem_object *pctx;