| Message ID | cover.1664550870.git.thomas.lendacky@amd.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Qemu SEV reduced-phys-bits fixes | expand |
On 9/30/22 10:14, Tom Lendacky wrote: > This patch series fixes up and tries to remove some confusion around the > SEV reduced-phys-bits parameter. > > Based on the "AMD64 Architecture Programmer's Manual Volume 2: System > Programming", section "15.34.6 Page Table Support" [1], a guest should > only ever see a maximum of 1 bit of physical address space reduction. > > - Update the documentation, to change the default value from 5 to 1. > - Update the validation of the parameter to ensure the parameter value > is within the range of the CPUID field that it is reported in. To allow > for backwards compatibility, especially to support the previously > documented value of 5, allow the full range of values from 1 to 63 > (0 was never allowed). > - Update the setting of CPUID 0x8000001F_EBX to limit the values to the > field width that they are setting as an additional safeguard. > > [1] https://www.amd.com/system/files/TechDocs/24593.pdf Ping, any concerns with this series? Thanks, Tom > > Tom Lendacky (4): > qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 > qemu-options.hx: Update the reduced-phys-bits documentation > i386/sev: Update checks and information related to reduced-phys-bits > i386/cpu: Update how the EBX register of CPUID 0x8000001F is set > > qapi/misc-target.json | 2 +- > qemu-options.hx | 4 ++-- > target/i386/cpu.c | 4 ++-- > target/i386/sev.c | 17 ++++++++++++++--- > 4 files changed, 19 insertions(+), 8 deletions(-) >
On Wed, Jan 04, 2023 at 12:13:09PM -0600, Tom Lendacky wrote: > On 9/30/22 10:14, Tom Lendacky wrote: > > This patch series fixes up and tries to remove some confusion around the > > SEV reduced-phys-bits parameter. > > > > Based on the "AMD64 Architecture Programmer's Manual Volume 2: System > > Programming", section "15.34.6 Page Table Support" [1], a guest should > > only ever see a maximum of 1 bit of physical address space reduction. > > > > - Update the documentation, to change the default value from 5 to 1. > > - Update the validation of the parameter to ensure the parameter value > > is within the range of the CPUID field that it is reported in. To allow > > for backwards compatibility, especially to support the previously > > documented value of 5, allow the full range of values from 1 to 63 > > (0 was never allowed). > > - Update the setting of CPUID 0x8000001F_EBX to limit the values to the > > field width that they are setting as an additional safeguard. > > > > [1] https://www.amd.com/system/files/TechDocs/24593.pdf > > Ping, any concerns with this series? Looks like you got postive review from David in Oct, so this needs one of the x86 maintainers to queue the series. > > Tom Lendacky (4): > > qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 > > qemu-options.hx: Update the reduced-phys-bits documentation > > i386/sev: Update checks and information related to reduced-phys-bits > > i386/cpu: Update how the EBX register of CPUID 0x8000001F is set > > > > qapi/misc-target.json | 2 +- > > qemu-options.hx | 4 ++-- > > target/i386/cpu.c | 4 ++-- > > target/i386/sev.c | 17 ++++++++++++++--- > > 4 files changed, 19 insertions(+), 8 deletions(-) > > > With regards, Daniel
Queued, thanks. Paolo