| Message ID | 20230420124050.3617608-4-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Add support for C20 phy | expand |
On Thu, Apr 20, 2023 at 03:40:40PM +0300, Mika Kahola wrote: > As we already do with C10 chip, let's dump the pll > hw state for C20 as well. > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++ > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > 3 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 61428c5145e5..144474540ef4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, > } > } > > +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, > + const struct intel_c20pll_state *hw_state) > +{ > + int i; > + > + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); > + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", > + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); > + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", > + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); > + > + if (intel_c20_use_mplla(hw_state->clock)) { > + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) > + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); > + } else { > + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) > + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); > + } > +} > + > static u8 intel_c20_get_dp_rate(u32 clock) > { > switch (clock) { > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > index 9760c6292c81..c643aae27bac 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > @@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state, > struct intel_crtc_state *new_crtc_state); > void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, > struct intel_c20pll_state *pll_state); > +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, > + const struct intel_c20pll_state *hw_state); > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 44f07011245b..d414dd8c26bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder, > intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10); > } else { > intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20); > + intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20); > } > > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); > -- > 2.34.1 >
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika > Kahola > Sent: Thursday, April 20, 2023 6:11 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 03/13] drm/i915/mtl: Dump C20 pll hw state > > As we already do with C10 chip, let's dump the pll hw state for C20 as well. > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++ > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > 3 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 61428c5145e5..144474540ef4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct > intel_encoder *encoder, > } > } > > +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, > + const struct intel_c20pll_state *hw_state) { > + int i; > + > + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); > + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = > 0x%.4x\n", > + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); > + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, > cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", > + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], > +hw_state->cmn[3]); > + > + if (intel_c20_use_mplla(hw_state->clock)) { > + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) > + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", > i, hw_state->mplla[i]); > + } else { > + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) > + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", > i, hw_state->mpllb[i]); > + } > +} > + > static u8 intel_c20_get_dp_rate(u32 clock) { > switch (clock) { > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > index 9760c6292c81..c643aae27bac 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h > @@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state > *state, > struct intel_crtc_state *new_crtc_state); void > intel_c20pll_readout_hw_state(struct intel_encoder *encoder, > struct intel_c20pll_state *pll_state); > +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, > + const struct intel_c20pll_state *hw_state); > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 44f07011245b..d414dd8c26bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder > *encoder, > intel_c10pll_dump_hw_state(i915, &crtc_state- > >cx0pll_state.c10); > } else { > intel_c20pll_readout_hw_state(encoder, &crtc_state- > >cx0pll_state.c20); > + intel_c20pll_dump_hw_state(i915, &crtc_state- > >cx0pll_state.c20); > } > > crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, > &crtc_state->cx0pll_state.c10); > -- > 2.34.1
Hi Mika, > + > + if (intel_c20_use_mplla(hw_state->clock)) { > + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) > + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); > + } else { > + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) > + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); > + } if you're going to resend it, brackets are nnot needed here. Andi
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 61428c5145e5..144474540ef4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2035,6 +2035,26 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, } } +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c20pll_state *hw_state) +{ + int i; + + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); + + if (intel_c20_use_mplla(hw_state->clock)) { + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); + } else { + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); + } +} + static u8 intel_c20_get_dp_rate(u32 clock) { switch (clock) { diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 9760c6292c81..c643aae27bac 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -32,6 +32,8 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state); void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c20pll_state *pll_state); +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c20pll_state *hw_state); void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 44f07011245b..d414dd8c26bf 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3858,6 +3858,7 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder, intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10); } else { intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20); + intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20); } crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
As we already do with C10 chip, let's dump the pll hw state for C20 as well. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 3 files changed, 23 insertions(+)