[5.10.y-cip,00/33] Add RZ/V2M support

Message ID	20230421071729.130347-1-biju.das.jz@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Fabrizio Castro <fabrizio.castro.jz@renesas.com> Subject: [PATCH 5.10.y-cip 00/33] Add RZ/V2M support Date: Fri, 21 Apr 2023 08:16:56 +0100 Message-Id: <20230421071729.130347-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add RZ/V2M support \| expand [5.10.y-cip,00/33] Add RZ/V2M support [5.10.y-cip,01/33] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings [5.10.y-cip,02/33] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers [5.10.y-cip,03/33] serial: 8250: extend compile-test coverage [5.10.y-cip,04/33] serial: 8250: SERIAL_8250_EM should depend on ARCH_RENESAS [5.10.y-cip,05/33] serial: 8250: Make SERIAL_8250_EM available for arm64 systems [5.10.y-cip,06/33] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board [5.10.y-cip,07/33] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration [5.10.y-cip,08/33] soc: renesas: Identify RZ/V2M SoC [5.10.y-cip,09/33] soc: renesas: Add RZ/V2M (R9A09G011) config option [5.10.y-cip,10/33] arm64: defconfig: Enable Renesas RZ/V2M SoC [5.10.y-cip,11/33] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions [5.10.y-cip,12/33] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC [5.10.y-cip,13/33] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro [5.10.y-cip,14/33] clk: renesas: rzg2l: Add read only versions of the clk macros [5.10.y-cip,15/33] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers [5.10.y-cip,16/33] clk: renesas: rzg2l: Make use of CLK_MON registers optional [5.10.y-cip,17/33] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg [5.10.y-cip,18/33] clk: renesas: Add RZ/V2M support using the rzg2l driver [5.10.y-cip,19/33] clk: renesas: r9a09g011: Add eth clock and reset entries [5.10.y-cip,20/33] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC [5.10.y-cip,21/33] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK [5.10.y-cip,22/33] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC [5.10.y-cip,23/33] ravb: Separate handling of irq enable/disable regs into feature [5.10.y-cip,24/33] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs [5.10.y-cip,25/33] ravb: Use separate clock for gPTP [5.10.y-cip,26/33] ravb: Add support for RZ/V2M [5.10.y-cip,27/33] arm64: dts: renesas: r9a09g011: Add ethernet nodes [5.10.y-cip,28/33] arm64: dts: renesas: rzv2mevk2: Enable ethernet [5.10.y-cip,29/33] clk: renesas: r9a09g011: Add PFC clock and reset entries [5.10.y-cip,30/33] dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl [5.10.y-cip,31/33] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled [5.10.y-cip,32/33] pinctrl: renesas: Add RZ/V2M pin and gpio controller driver [5.10.y-cip,33/33] arm64: dts: renesas: r9a09g011: Add pinctrl node

Message ID

20230421071729.130347-1-biju.das.jz@bp.renesas.com (mailing list archive)

Headers

From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: [PATCH 5.10.y-cip 00/33] Add RZ/V2M support
Date: Fri, 21 Apr 2023 08:16:56 +0100
Message-Id: <20230421071729.130347-1-biju.das.jz@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add RZ/V2M support | expand

Message

Biju Das April 21, 2023, 7:16 a.m. UTC

This patch series aims to add Basic board support for EVK
based on RZ/V2M SoC.

All these patches are cherry-picked from the mainline.

Subsequent patch series will add more functionality to this platform.

RZ/V2M EVK logs:
root@rzv2m:~# cat /sys/devices/soc0/family
RZ/V2M
root@rzv2m:~# cat /sys/devices/soc0/machine
RZ/V2M Evaluation Kit 2.0
root@rzv2m:~# cat /sys/devices/soc0/soc_id
r9a09g011
root@rzv2m:~# dmesg  | grep Detect
[    0.002815] Detected Renesas RZ/V2M r9a09g011

Geert Uytterhoeven (1):
  serial: 8250: SERIAL_8250_EM should depend on ARCH_RENESAS

Johan Hovold (1):
  serial: 8250: extend compile-test coverage

Lad Prabhakar (1):
  pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled

Phil Edworthy (30):
  dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings
  dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the
    registers
  serial: 8250: Make SERIAL_8250_EM available for arm64 systems
  dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board
  dt-bindings: arm: renesas: Document Renesas RZ/V2M System
    Configuration
  soc: renesas: Identify RZ/V2M SoC
  soc: renesas: Add RZ/V2M (R9A09G011) config option
  arm64: defconfig: Enable Renesas RZ/V2M SoC
  dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
  dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
  clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
  clk: renesas: rzg2l: Add read only versions of the clk macros
  clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
  clk: renesas: rzg2l: Make use of CLK_MON registers optional
  clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
  clk: renesas: Add RZ/V2M support using the rzg2l driver
  clk: renesas: r9a09g011: Add eth clock and reset entries
  arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC
  arm64: dts: renesas: Add initial device tree for RZ/V2M EVK
  dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
  ravb: Separate handling of irq enable/disable regs into feature
  ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
  ravb: Use separate clock for gPTP
  ravb: Add support for RZ/V2M
  arm64: dts: renesas: r9a09g011: Add ethernet nodes
  arm64: dts: renesas: rzv2mevk2: Enable ethernet
  clk: renesas: r9a09g011: Add PFC clock and reset entries
  dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl
  pinctrl: renesas: Add RZ/V2M pin and gpio controller driver
  arm64: dts: renesas: r9a09g011: Add pinctrl node

 .../devicetree/bindings/arm/renesas.yaml      |    6 +
 .../bindings/clock/renesas,rzg2l-cpg.yaml     |   13 +-
 .../bindings/net/renesas,etheravb.yaml        |   82 +-
 .../pinctrl/renesas,rzv2m-pinctrl.yaml        |  170 +++
 .../bindings/serial/renesas,em-uart.yaml      |   37 +-
 .../soc/renesas/renesas,r9a09g011-sys.yaml    |   43 +
 arch/arm64/boot/dts/renesas/Makefile          |    2 +
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    |   58 +
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    |  194 +++
 arch/arm64/configs/defconfig                  |    2 +
 drivers/clk/renesas/Kconfig                   |    5 +
 drivers/clk/renesas/Makefile                  |    1 +
 drivers/clk/renesas/r9a07g043-cpg.c           |   29 +-
 drivers/clk/renesas/r9a07g044-cpg.c           |   37 +-
 drivers/clk/renesas/r9a09g011-cpg.c           |  174 +++
 drivers/clk/renesas/rzg2l-cpg.c               |   24 +-
 drivers/clk/renesas/rzg2l-cpg.h               |   41 +-
 drivers/net/ethernet/renesas/ravb.h           |    6 +
 drivers/net/ethernet/renesas/ravb_main.c      |  109 +-
 drivers/net/ethernet/renesas/ravb_ptp.c       |    6 +-
 drivers/pinctrl/renesas/Kconfig               |   17 +-
 drivers/pinctrl/renesas/Makefile              |    1 +
 drivers/pinctrl/renesas/pinctrl-rzv2m.c       | 1119 +++++++++++++++++
 drivers/soc/renesas/Kconfig                   |    7 +
 drivers/soc/renesas/renesas-soc.c             |   22 +
 drivers/tty/serial/8250/Kconfig               |    3 +-
 include/dt-bindings/clock/r9a09g011-cpg.h     |  352 ++++++
 include/dt-bindings/pinctrl/rzv2m-pinctrl.h   |   23 +
 28 files changed, 2481 insertions(+), 102 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g011-sys.yaml
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi
 create mode 100644 drivers/clk/renesas/r9a09g011-cpg.c
 create mode 100644 drivers/pinctrl/renesas/pinctrl-rzv2m.c
 create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
 create mode 100644 include/dt-bindings/pinctrl/rzv2m-pinctrl.h

Comments

Pavel Machek April 21, 2023, 10:54 a.m. UTC | #1

Hi!

> All these patches are cherry-picked from the mainline.

Ok. Well likely need to backport these to 6.1.X, too, but I suppose
that will not be hard.

I went through the patches and submitted them to testing. I can apply
them if there are no other comments.

Thank you and best regards,
								Pavel

Biju Das April 21, 2023, 11:18 a.m. UTC | #2

Hi Pavel,

> Subject: Re: [PATCH 5.10.y-cip 00/33] Add RZ/V2M support
> 
> Hi!
> 
> > All these patches are cherry-picked from the mainline.
> 
> Ok. Well likely need to backport these to 6.1.X, too, but I suppose that
> will not be hard.

OK, we will look into it when CIP publishes a 6.1 branch.

Cheers,
Biju

Pavel Machek April 25, 2023, 9:13 a.m. UTC | #3

Hi!

> > > All these patches are cherry-picked from the mainline.
> > 
> > Ok. Well likely need to backport these to 6.1.X, too, but I suppose that
> > will not be hard.
> 
> OK, we will look into it when CIP publishes a 6.1 branch.

Thank you, applied.

Best regards,
								Pavel