| Message ID | 20230418111612.19479-6-ddrokosov@sberdevices.ru (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: meson: support Amlogic A1 USB OTG controller | expand |
On Tue, Apr 18, 2023 at 1:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote: [...] > + usb2_phy1: phy@4000 { > + compatible = "amlogic,a1-usb2-phy"; > + clocks = <&clkc CLKID_USB_PHY_IN>; > + clock-names = "xtal"; Out of curiosity since there's also a CLKID_USB_PHY clock (which is used for the dwc3 controller below): Do we know that this part of the clock hierarchy is correct? I have no way to check this myself, so I'm curious if you could verify this somehow. [...] > + dwc2: usb@ff500000 { > + compatible = "amlogic,meson-a1-usb", "snps,dwc2"; > + reg = <0x0 0xff500000 0x0 0x40000>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb2_phy1>; > + phy-names = "usb2_phy"; Documentation/devicetree/bindings/usb/dwc2.yaml only allows a "usb2-phy" (dash instead of underscore). [...] > + dwc3: usb@ff400000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0xff400000 0x0 0x100000>; Note to self: interesting that Amlogic swapped the register location of the dwc2 and dwc3 controllers since the G12 generation.
On Sun, Apr 23, 2023 at 07:51:31PM +0200, Martin Blumenstingl wrote: > On Tue, Apr 18, 2023 at 1:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote: > [...] > > + usb2_phy1: phy@4000 { > > + compatible = "amlogic,a1-usb2-phy"; > > + clocks = <&clkc CLKID_USB_PHY_IN>; > > + clock-names = "xtal"; > Out of curiosity since there's also a CLKID_USB_PHY clock (which is > used for the dwc3 controller below): > Do we know that this part of the clock hierarchy is correct? I have no > way to check this myself, so I'm curious if you could verify this > somehow. > > [...] I've developed a clock driver for A1 and verified it against the Amlogic custom driver and datasheet. As you pointed out, there are indeed two USB phy clocks. They are labeled as follows in my clock driver: * CLKID_USB_PHY_IN (xtal -> usb_phy gated clock) - the phy input clock * CLKID_USB_PHY (SYS_CLK_EN based gate) - the synopsys IP gated clock The current representation of the USB phy clocks is solely based on my technical opinion, as the datasheet does not provide any detailed information about them. Clock driver: https://lore.kernel.org/all/20230405195927.13487-1-ddrokosov@sberdevices.ru/ > > + dwc2: usb@ff500000 { > > + compatible = "amlogic,meson-a1-usb", "snps,dwc2"; > > + reg = <0x0 0xff500000 0x0 0x40000>; > > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&usb2_phy1>; > > + phy-names = "usb2_phy"; > Documentation/devicetree/bindings/usb/dwc2.yaml only allows a > "usb2-phy" (dash instead of underscore). > > [...] Ah, my fault.. > > + dwc3: usb@ff400000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xff400000 0x0 0x100000>; > Note to self: interesting that Amlogic swapped the register location > of the dwc2 and dwc3 controllers since the G12 generation. Indeed, during the bringup process, I was surprised to discover that the dwc2 engine wasn't starting properly. It was quite unexpected, but also admittedly intriguing as I delved into the issue and tried to understand the root cause.
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index ae7d39cff07a..02af0aac6780 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/gpio/meson-a1-gpio.h> #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> #include <dt-bindings/clock/amlogic,a1-clkc.h> +#include <dt-bindings/power/meson-a1-power.h> +#include <dt-bindings/reset/amlogic,meson-a1-reset.h> / { compatible = "amlogic,a1"; @@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@0440 { amlogic,channel-interrupts = <49 50 51 52 53 54 55 56>; }; + + usb2_phy1: phy@4000 { + compatible = "amlogic,a1-usb2-phy"; + clocks = <&clkc CLKID_USB_PHY_IN>; + clock-names = "xtal"; + reg = <0x0 0x4000 0x0 0x60>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; }; gic: interrupt-controller@ff901000 { @@ -192,6 +205,52 @@ spifc: spi@fd000400 { #size-cells = <0>; status = "disabled"; }; + + usb: usb@fe004400 { + status = "disabled"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xfe004400 0x0 0xa0>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB_CTRL>, + <&clkc CLKID_USB_BUS>, + <&clkc CLKID_USB_CTRL_IN>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + reset-name = "usb_ctrl"; + + dr_mode = "otg"; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + dwc2: usb@ff500000 { + compatible = "amlogic,meson-a1-usb", "snps,dwc2"; + reg = <0x0 0xff500000 0x0 0x40000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy1>; + phy-names = "usb2_phy"; + clocks = <&clkc CLKID_USB_PHY>; + clock-names = "otg"; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,parkmode-disable-ss-quirk; + }; + }; }; timer {