diff mbox series

[5/5] drm/i915/guc: Capture list clean up - 4

Message ID 20230406222617.790484-6-John.C.Harrison@Intel.com (mailing list archive)
State New, archived
Headers show
Series Improvements to GuC error capture list processing | expand

Commit Message

John Harrison April 6, 2023, 10:26 p.m. UTC 
From: John Harrison <John.C.Harrison@Intel.com>

Don't use GEN9 as a prefix for register lists that contain all GEN8
registers.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Alan Previn April 25, 2023, 7:10 p.m. UTC | #1 
On Thu, 2023-04-06 at 15:26 -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Don't use GEN9 as a prefix for register lists that contain all GEN8
> registers.
alan:snip

alan: This patch as a stand-along looks good, so I'll provide the RB but take note of the comment below
that should be reflected by decision on the review comments of patch #1 so this patch might
change from GEN9_foo-from-patch-1 to GEN8_foo-from-patch-1.

Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>

> -/* GEN9 - Global */
> +/* GEN8 - Global */
>  static const struct __guc_mmio_reg_descr default_global_regs[] = {
>  	COMMON_BASE_GLOBAL,
> -	COMMON_GEN9BASE_GLOBAL,
> -	GEN9_GLOBAL,
> +	COMMON_GEN8BASE_GLOBAL,
> +	GEN8_GLOBAL,
alan: see patch comment about "COMMON_GLOBAL" vs "GLOBAL" confusion.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index fbd0be4afc6d5..c1a75a2d17f1e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -30,12 +30,12 @@ 
 #define COMMON_BASE_GLOBAL \
 	{ FORCEWAKE_MT,             0,      0, "FORCEWAKE" }
 
-#define COMMON_GEN9BASE_GLOBAL \
+#define COMMON_GEN8BASE_GLOBAL \
 	{ ERROR_GEN6,               0,      0, "ERROR_GEN6" }, \
 	{ DONE_REG,                 0,      0, "DONE_REG" }, \
 	{ HSW_GTT_CACHE_EN,         0,      0, "HSW_GTT_CACHE_EN" }
 
-#define GEN9_GLOBAL \
+#define GEN8_GLOBAL \
 	{ GEN8_FAULT_TLB_DATA0,     0,      0, "GEN8_FAULT_TLB_DATA0" }, \
 	{ GEN8_FAULT_TLB_DATA1,     0,      0, "GEN8_FAULT_TLB_DATA1" }
 
@@ -99,7 +99,7 @@ 
 /* XE_LP Global */
 static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
 	COMMON_BASE_GLOBAL,
-	COMMON_GEN9BASE_GLOBAL,
+	COMMON_GEN8BASE_GLOBAL,
 	COMMON_GEN12BASE_GLOBAL,
 };
 
@@ -140,11 +140,11 @@  static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
 	COMMON_BASE_ENGINE_INSTANCE,
 };
 
-/* GEN9 - Global */
+/* GEN8 - Global */
 static const struct __guc_mmio_reg_descr default_global_regs[] = {
 	COMMON_BASE_GLOBAL,
-	COMMON_GEN9BASE_GLOBAL,
-	GEN9_GLOBAL,
+	COMMON_GEN8BASE_GLOBAL,
+	GEN8_GLOBAL,
 };
 
 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {