| Message ID | 20230428190609.3239486-4-evan@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V: Export Zba, Zbb to usermode via hwprobe | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 3ec1aafb0ff9 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 579 this patch: 579 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 1260 this patch: 1260 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Prefer using the BIT macro |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: > Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These > are accurately reported per CPU. > > Signed-off-by: Evan Green <evan@rivosinc.com> > > --- > > Documentation/riscv/hwprobe.rst | 7 +++++ > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- > 3 files changed, 45 insertions(+), 7 deletions(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..21f444a38359 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -64,6 +64,13 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is > + supported, as defined in version 1.0 of the Bit-Manipulation ISA > + extensions. > + > + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, so I assume this is a copy-paste mistake. Also, s/supporte/supported. Otherwise, looks fine. Cheers, Conor. > + in version 1.0 of the Bit-Manipulation ISA extensions. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..ef3b060d4e8d 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -25,6 +25,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) > +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..adfcb6b64db7 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, > pair->value = id; > } > > +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > + const struct cpumask *cpus) > +{ > + int cpu; > + u64 missing = 0; > + > + pair->value = 0; > + if (has_fpu()) > + pair->value |= RISCV_HWPROBE_IMA_FD; > + > + if (riscv_isa_extension_available(NULL, c)) > + pair->value |= RISCV_HWPROBE_IMA_C; > + > + /* > + * Loop through and record extensions that 1) anyone has, and 2) anyone > + * doesn't have. > + */ > + for_each_cpu(cpu, cpus) { > + struct riscv_isainfo *isainfo = &hart_isa[cpu]; > + > + if (riscv_isa_extension_available(isainfo->isa, ZBA)) > + pair->value |= RISCV_HWPROBE_EXT_ZBA; > + else > + missing |= RISCV_HWPROBE_EXT_ZBA; > + > + if (riscv_isa_extension_available(isainfo->isa, ZBB)) > + pair->value |= RISCV_HWPROBE_EXT_ZBB; > + else > + missing |= RISCV_HWPROBE_EXT_ZBB; > + } > + > + /* Now turn off reporting features if any CPU is missing it. */ > + pair->value &= ~missing; > +} > + > static u64 hwprobe_misaligned(const struct cpumask *cpus) > { > int cpu; > @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > break; > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > - pair->value = 0; > - if (has_fpu()) > - pair->value |= RISCV_HWPROBE_IMA_FD; > - > - if (riscv_isa_extension_available(NULL, c)) > - pair->value |= RISCV_HWPROBE_IMA_C; > - > + hwprobe_isa_ext0(pair, cpus); > break; > > case RISCV_HWPROBE_KEY_CPUPERF_0: > -- > 2.25.1 >
On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote: > On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: >> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These >> are accurately reported per CPU. >> >> Signed-off-by: Evan Green <evan@rivosinc.com> >> >> --- >> >> Documentation/riscv/hwprobe.rst | 7 +++++ >> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ >> arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- >> 3 files changed, 45 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst >> index 9f0dd62dcb5d..21f444a38359 100644 >> --- a/Documentation/riscv/hwprobe.rst >> +++ b/Documentation/riscv/hwprobe.rst >> @@ -64,6 +64,13 @@ The following keys are defined: >> * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined >> by version 2.2 of the RISC-V ISA manual. >> >> + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is >> + supported, as defined in version 1.0 of the Bit-Manipulation ISA >> + extensions. >> + >> + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined > > Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, > so I assume this is a copy-paste mistake. Looks like it. Either way this was too late for the current merge window, so no big deal. > > Also, s/supporte/supported. > > Otherwise, looks fine. > Cheers, > Conor. > >> + in version 1.0 of the Bit-Manipulation ISA extensions. >> + >> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance >> information about the selected set of processors. >> >> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h >> index 8d745a4ad8a2..ef3b060d4e8d 100644 >> --- a/arch/riscv/include/uapi/asm/hwprobe.h >> +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> @@ -25,6 +25,8 @@ struct riscv_hwprobe { >> #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 >> #define RISCV_HWPROBE_IMA_FD (1 << 0) >> #define RISCV_HWPROBE_IMA_C (1 << 1) >> +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) >> +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) >> #define RISCV_HWPROBE_KEY_CPUPERF_0 5 >> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) >> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) >> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c >> index 5db29683ebee..adfcb6b64db7 100644 >> --- a/arch/riscv/kernel/sys_riscv.c >> +++ b/arch/riscv/kernel/sys_riscv.c >> @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, >> pair->value = id; >> } >> >> +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, >> + const struct cpumask *cpus) >> +{ >> + int cpu; >> + u64 missing = 0; >> + >> + pair->value = 0; >> + if (has_fpu()) >> + pair->value |= RISCV_HWPROBE_IMA_FD; >> + >> + if (riscv_isa_extension_available(NULL, c)) >> + pair->value |= RISCV_HWPROBE_IMA_C; >> + >> + /* >> + * Loop through and record extensions that 1) anyone has, and 2) anyone >> + * doesn't have. >> + */ >> + for_each_cpu(cpu, cpus) { >> + struct riscv_isainfo *isainfo = &hart_isa[cpu]; >> + >> + if (riscv_isa_extension_available(isainfo->isa, ZBA)) >> + pair->value |= RISCV_HWPROBE_EXT_ZBA; >> + else >> + missing |= RISCV_HWPROBE_EXT_ZBA; >> + >> + if (riscv_isa_extension_available(isainfo->isa, ZBB)) >> + pair->value |= RISCV_HWPROBE_EXT_ZBB; >> + else >> + missing |= RISCV_HWPROBE_EXT_ZBB; >> + } >> + >> + /* Now turn off reporting features if any CPU is missing it. */ >> + pair->value &= ~missing; >> +} >> + >> static u64 hwprobe_misaligned(const struct cpumask *cpus) >> { >> int cpu; >> @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, >> break; >> >> case RISCV_HWPROBE_KEY_IMA_EXT_0: >> - pair->value = 0; >> - if (has_fpu()) >> - pair->value |= RISCV_HWPROBE_IMA_FD; >> - >> - if (riscv_isa_extension_available(NULL, c)) >> - pair->value |= RISCV_HWPROBE_IMA_C; >> - >> + hwprobe_isa_ext0(pair, cpus); >> break; >> >> case RISCV_HWPROBE_KEY_CPUPERF_0: >> -- >> 2.25.1 >>
On Sat, Apr 29, 2023 at 1:07 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote: > > On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: > >> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These > >> are accurately reported per CPU. > >> > >> Signed-off-by: Evan Green <evan@rivosinc.com> > >> > >> --- > >> > >> Documentation/riscv/hwprobe.rst | 7 +++++ > >> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > >> arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- > >> 3 files changed, 45 insertions(+), 7 deletions(-) > >> > >> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > >> index 9f0dd62dcb5d..21f444a38359 100644 > >> --- a/Documentation/riscv/hwprobe.rst > >> +++ b/Documentation/riscv/hwprobe.rst > >> @@ -64,6 +64,13 @@ The following keys are defined: > >> * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > >> by version 2.2 of the RISC-V ISA manual. > >> > >> + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is > >> + supported, as defined in version 1.0 of the Bit-Manipulation ISA > >> + extensions. > >> + > >> + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined > > > > Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, > > so I assume this is a copy-paste mistake. > > Looks like it. Either way this was too late for the current merge > window, so no big deal. Copypasta! I'll fix it. -Evan
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..21f444a38359 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..ef3b060d4e8d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..adfcb6b64db7 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value = id; } +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + int cpu; + u64 missing = 0; + + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |= RISCV_HWPROBE_IMA_C; + + /* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + */ + for_each_cpu(cpu, cpus) { + struct riscv_isainfo *isainfo = &hart_isa[cpu]; + + if (riscv_isa_extension_available(isainfo->isa, ZBA)) + pair->value |= RISCV_HWPROBE_EXT_ZBA; + else + missing |= RISCV_HWPROBE_EXT_ZBA; + + if (riscv_isa_extension_available(isainfo->isa, ZBB)) + pair->value |= RISCV_HWPROBE_EXT_ZBB; + else + missing |= RISCV_HWPROBE_EXT_ZBB; + } + + /* Now turn off reporting features if any CPU is missing it. */ + pair->value &= ~missing; +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, break; case RISCV_HWPROBE_KEY_IMA_EXT_0: - pair->value = 0; - if (has_fpu()) - pair->value |= RISCV_HWPROBE_IMA_FD; - - if (riscv_isa_extension_available(NULL, c)) - pair->value |= RISCV_HWPROBE_IMA_C; - + hwprobe_isa_ext0(pair, cpus); break; case RISCV_HWPROBE_KEY_CPUPERF_0:
Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These are accurately reported per CPU. Signed-off-by: Evan Green <evan@rivosinc.com> --- Documentation/riscv/hwprobe.rst | 7 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- 3 files changed, 45 insertions(+), 7 deletions(-)