| Message ID | 1683144639-26614-5-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | add DSC 1.2 dpu supports | expand |
On 2023-05-03 13:10:36, Kuogee Hsieh wrote: > During DSC setup, the crossbar mux need to be programmed to engage > DSC to specified PINGPONG. Hence during tear down, the crossbar mux > need to be reset to disengage DSC from PINGPONG. 0X0F is written to > reset crossbar mux. It is not relevant to hw_pp->idx. This patch add > PINGPONG_NONE to serve as disable to reset crossbar mux. > > Changes in v4: > -- more details to commit text As requested in v3, this doesn't adequately explain that all you're doing is **removing `bool enable`** so that this function becomes simpler to call in the disable scenario without coming up with a random dpu_pingpong value that's irrelevant when enable=false. How about the following wording: drm/msm/dpu: Introduce PINGPONG_NONE to disconnect DSC from PINGPONG Disabling the crossbar mux between DSC and PINGPONG currently requires a bogus enum dpu_pingpong value to be passed when calling dsc_bind_pingpong_blk() with enable=false, even though the register value written is independent of the current PINGPONG block. Replace that `bool enable` parameter with a new PINGPONG_NONE dpu_pingpong flag that triggers the write of the "special" 0xF "crossbar disabled" value to the register instead. And don't forget to fix the log statement below. <snip> > DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n", > - enable ? "Binding" : "Unbinding", > + pp ? "Binding" : "Unbinding", > hw_dsc->idx - DSC_0, > - enable ? "to" : "from", > + pp ? "to" : "from", > pp - PINGPONG_0); This wasn't adjusted, see v3 review. - Marijn
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1dc5dbe..d9ad334 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1839,7 +1839,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc, hw_pp->ops.setup_dsc(hw_pp); if (hw_dsc->ops.dsc_bind_pingpong_blk) - hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, true, hw_pp->idx); + hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); if (hw_pp->ops.enable_dsc) hw_pp->ops.enable_dsc(hw_pp); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 4a6bbcc..3e68d47 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -157,7 +157,6 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, static void dpu_hw_dsc_bind_pingpong_blk( struct dpu_hw_dsc *hw_dsc, - bool enable, const enum dpu_pingpong pp) { struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; @@ -166,13 +165,13 @@ static void dpu_hw_dsc_bind_pingpong_blk( dsc_ctl_offset = DSC_CTL(hw_dsc->idx); - if (enable) + if (pp) mux_cfg = (pp - PINGPONG_0) & 0x7; DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n", - enable ? "Binding" : "Unbinding", + pp ? "Binding" : "Unbinding", hw_dsc->idx - DSC_0, - enable ? "to" : "from", + pp ? "to" : "from", pp - PINGPONG_0); DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h index 287ec5f..138080a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -44,7 +44,6 @@ struct dpu_hw_dsc_ops { struct drm_dsc_config *dsc); void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc, - bool enable, enum dpu_pingpong pp); }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 2d9192a..56826a9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -191,7 +191,8 @@ enum dpu_dsc { }; enum dpu_pingpong { - PINGPONG_0 = 1, + PINGPONG_NONE, + PINGPONG_0, PINGPONG_1, PINGPONG_2, PINGPONG_3,