Message ID | 20230504080526.133149-2-n-francis@ti.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add support for ESM | expand |
On 04/05/2023 10:05, Neha Malcom Francis wrote: > Document the binding for TI K3 ESM (Error Signaling Module) block. > > Signed-off-by: Neha Malcom Francis <n-francis@ti.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Thanks. Best regards, Krzysztof
On 10:11-20230504, Krzysztof Kozlowski wrote: > On 04/05/2023 10:05, Neha Malcom Francis wrote: > > Document the binding for TI K3 ESM (Error Signaling Module) block. > > > > Signed-off-by: Neha Malcom Francis <n-francis@ti.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > To make sure we are'nt stepping on toes: Krzysztof: is it OK to pick this up via SoC tree?
On 04/05/2023 13:51, Nishanth Menon wrote: > On 10:11-20230504, Krzysztof Kozlowski wrote: >> On 04/05/2023 10:05, Neha Malcom Francis wrote: >>> Document the binding for TI K3 ESM (Error Signaling Module) block. >>> >>> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> > To make sure we are'nt stepping on toes: > Krzysztof: is it OK to pick this up via SoC tree? Yes, please go ahead. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml new file mode 100644 index 000000000000..0c9a8444844c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 ESM + +maintainers: + - Neha Malcom Francis <n-francis@ti.com> + +description: + The ESM (Error Signaling Module) is an IP block on TI K3 devices + that allows handling of safety events somewhat similar to what interrupt + controller would do. The safety signals have their separate paths within + the SoC, and they are handled by the ESM, which routes them to the proper + destination, which can be system reset, interrupt controller, etc. In the + simplest configuration the signals are just routed to reset the SoC. + +properties: + compatible: + const: ti,j721e-esm + + reg: + maxItems: 1 + + ti,esm-pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + integer array of ESM interrupt pins to route to external event pin + which can be used to reset the SoC. + minItems: 1 + maxItems: 255 + +required: + - compatible + - reg + - ti,esm-pins + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; + };